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33903 Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc |
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33903 Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 104 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 53 33903/4/5 FAIL SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN SAFE Mode B1, B2 and B3 Illustration Figure 34 illustrates the event, and consequences when SAFE Mode B1, B2, or B3 is selected via the appropriate debug resistor or SPI configuration. DBG resistor => safe state B1 VDD RST SAFE CAN bus CAN bus idle time I/O-1 I/O-1 high to low transition DBG resistor => safe state B2 DBG resistor => safe state B3 CAN bus CAN bus idle time I/O-1 I/O-1 high to low transition step 2: RST VDD failure event, i.e. watchdog SAFE OFF state ON state 8 x 256 ms delay time to enter in SAFE Mode to evaluate resistor at the DBG pin and monitor ECU external events 1st 8th 2nd step 1: Failure illustration RST VDD failure event, VDD low SAFE OFF state ON state 100 ms delay time to enter in SAFE Mode to evaluate resistor at DBG pin and monitor ECU external events VDD_UV TH 100 ms GND RST VDD failure event, Reset s/c GND SAFE OFF state ON state 100 ms deglitcher time to activate SAFE and enter in SAFE Mode to evaluate resistor at DBG pin and monitor ECU external events 2.5 V 100 ms VDD RST SAFE VDD OFF RST SAFE VDD If VDD failure recovered VDD < VDD_UV TH VDD OFF GND step 3: Consequences for VDD If Reset s/c GND recovered Behavior illustration for the safe state B (RDG > 10 kohm) ECU external event to RDBG resistor or disable VDD based on SPI configuration Exclusive detection of Figure 34. SAFE Modes B1, B2, or B3 Behavior Illustration |
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