33903 datasheet(56/104 Pages) FREESCALE

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CANL

CANH

Internal Wake-Up signal

Dominant

CAN

Pulse # 1

Dominant

Pulse # 2

tCAN WU1-F

Can Wake-Up detected

bus

Internal differential Wake-Up receiver signal

Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

CAN INTERFACE

CAN INTERFACE DESCRIPTION

Figure 37. Single Dominant Pulse Wake-up

Pattern Wake-up

In order to Wake-Up the CAN interface, the Wake-Up

receiver must receive a series of three consecutive valid

dominant pulses, by default when the CANWU bit is low.

CANWU bit can be set high by SPI and the Wake-Up will

occur after a single pulse duration of 2.0

μs (typically).

A valid dominant pulse should be longer than 500 ns. The

three pulses should occur in a time frame of 120

μs, to be

considered valid. When three pulses meet these conditions,

the wake signal is detected. This is illustrated by the following

figure.

CANL

CANH

Internal Wake-Up signal

Dominant

Internal differential Wake-Up receiver signal

CAN

Pulse # 1

Dominant

Pulse # 2

Dominant

Pulse # 3

Dominant

Pulse # 4

tCAN WU3-F

tCAN WU3-TO

Dominant Pulse # n: duration 1 or multiple dominant bits

Can Wake-Up detected

bus

Figure 38. Pattern Wake-up - Multiple Dominant Detection

BUS TERMINATION

The device supports the two main types of bus

terminations:

• Differential termination resistors between CANH and

CANL lines.

• SPLIT termination concept, with the mid point of the

differential termination connected to GND through a

capacitor and to the SPLIT pin.

• In application, the device can also be used without

termination.

• Figure 39 illustrates some of the most common

terminations.

33903 Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc

33903 Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc

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