33903 datasheet(52/104 Pages) FREESCALE

52 / 104 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

FAIL SAFE OPERATION

BEHAVIOR AT POWER UP AND POWER DOWN

SAFE Mode A Illustration

Figure 33 illustrates the event and consequences when SAFE Mode A is selected via the appropriate debug resistor or SPI

configuration.

RST

VDD

failure event, i.e. watchdog

SAFE

OFF state ON state

8 x 256 ms delay time to enter in SAFE Mode

VDD

RST

SAFE

to evaluate resistor at DBG pin

and monitor ECU external events

1st

8th

2nd

Behavior Illustration for Safe State A (RDG < 6.0 kohm), or Selection by the SPI

step 1: Failure illustration

RST

VDD

failure event, VDD low

SAFE

OFF state ON state

100 ms delay time to enter in SAFE Mode

to evaluate resistor at DBG pin

and monitor ECU external events

VDD_UV TH

100ms

VDD

RST

SAFE

VDD < VDD_UV TH

GND

RST

VDD

failure event, Reset s/c GND

SAFE

OFF state

ON state

100 ms deglitcher time to activate SAFE and

enter in SAFE Mode to evaluate resistor at the DBG pin

and monitor ECU external events

2.5 V

100ms

VDD

RST

SAFE

step 2: Consequence on

VDD, RST and SAFE

Figure 33. SAFE Mode A Behavior Illustration

33903 Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc

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