33903 datasheet(62/104 Pages) FREESCALE

62 / 104 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

HIGH LEVEL OVERVIEW

SERIAL PERIPHERAL INTERFACE

HIGH LEVEL OVERVIEW

The device uses a 16 bits SPI, with the following

arrangements:

MOSI, Master Out Slave In bits:

• bits 15 and 14 (called C1 and C0) are control bits to

select the SPI operation mode (write control bit to

device register, read back of the control bits, read of

device flag).

• bit 13 to 9 (A4 to A0) to select the register address.

• bit 8 (P/N) has two functions: parity bit in write mode

(optional, = 0 if not used), Next bit ( = 1) in read mode.

• bit7 to 0 (D7 to D0): control bits

MISO, Master In Slave Out bits:

• bits 15 to 8 (S15 to S8) are device status bits

• bits 7 to 0 (Do7 to Do0) are either extended device

status bits, device internal control register content or

device flags.

The SPI implementation does not support daisy chain

capability.

Figure 43 is an overview of the SPI implementation.

Bit 15

Bit 13

Bit 11

Bit 12

Bit 10

Bit 14

Bit 9 Bit 8

Bit 7

Bit 5

Bit 3

Bit 4

Bit 2

Bit 6

Bit 1 Bit 0

control bits

Parity (optional) or

P/N

data

MOSI

S15

S13

S11

S14

Do7

Do5

Do3

Do4

Do2

Do6

Do1

Do0

S12

S10

MISO

Device Status

Extended Device Status, Register Control bits or Device Flags

Next bit = 1

SCLK

MOSI

MISO Tri-state

Tri-state

SPI Wave Form, and Signals Polarity

S15

S14

Do0

SCLK signal is low outside of CS active

CS active low. Must rise at end of 16 clocks,

MOSI and MISO data changed at SCLK rising edge

and sampled at falling edge. Msb first.

MISO tri-state outside of CS active

Don’t Care

for write commands, MOSI bits [15, 14] = ¬¨‚Ä†[0

Figure 43. SPI Overview

33903 Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc

33903 Datasheet(HTML) 62 Page - Freescale Semiconductor, Inc

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