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33903 Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc |
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33903 Datasheet(HTML) 68 Page - Freescale Semiconductor, Inc |
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68 / 104 page ![]() Analog Integrated Circuit Device Data 68 Freescale Semiconductor 33903/4/5 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING INIT REGISTERS Note: these registers can be written only in INIT Mode Table 15. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT Mode) MOSI First Byte [15-8] [b_15 b_14] 0_0101 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 101 P I/O-x sync VDDL rst[1] VDDL rst[0] VDD rstD[1] VDD rstD[0] VAUX5/3 Cyclic on[1] Cyclic on[0] Default state 1 0 0 0 0 0 0 0 Condition for default POR Bit Description b7 I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected 0 I/O-1 sense anytime 1 I/O-1 sense during I/O-0 activation b6, b5 VDDL RST[1] VDDL RST[0] - Select the VDD under-voltage threshold, to activate RESET pin and/or INT 00 Reset at approx 0.9 VDD. 01 INT at approx 0.9 VDD, Reset at approx 0.7 VDD 10 Reset at approx 0.7 VDD 11 Reset at approx 0.9 VDD. b4, b3 VDD RSTD[1] VDD RSTD[0] - Select the RESET pin low lev duration, after VDD rises above the VDD under-voltage threshold 00 1.0 ms 01 5.0 ms 10 10 ms 11 20 ms b2 [VAUX 5/3] - Select Vauxilary output voltage 0 VAUX = 3.3 V 1 VAUX = 5.0 V b1, b0 Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected 00 200 μs (typical value. Ref. to dynamic parameters for exact value) 01 400 μs (typical value. Ref. to dynamic parameters for exact value) 10 800 μs (typical value. Ref. to dynamic parameters for exact value) 11 1600 μs (typical value. Ref. to dynamic parameters for exact value) |
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