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ADV7180WBSTZ Datasheet(PDF) 105 Page - Analog Devices |
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ADV7180WBSTZ Datasheet(HTML) 105 Page - Analog Devices |
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105 / 120 page ![]() Data Sheet ADV7180 Rev. G | Page 105 of 120 User Sub Map Bit (Shading Indicates Default State) Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x86 VDP_GS_VPS_PDC_UTC_2 (read only) GS_VPS_PDC_UTC_BYTE_2[7:0] x x x x x x x x Decoded Gemstar/VPS/PDC/UTC data 0x87 VDP_GS_VPS_PDC_UTC_3 (read only) GS_VPS_PDC_UTC_BYTE_3[7:0] x x x x x x x x Decoded Gemstar/VPS/PDC/UTC data 0x88 VDP_VPS_PDC_UTC_4 (read only) VPS_PDC_UTC_BYTE_4[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x89 VDP_VPS_PDC_UTC_5 (read only) VPS_PDC_UTC_BYTE_5[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x8A VDP_VPS_PDC_UTC_6 (read only) VPS_PDC_UTC_BYTE_6[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x8B VDP_VPS_PDC_UTC_7 (read only) VPS_PDC_UTC_BYTE_7[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x8C VDP_VPS_PDC_UTC_8 (read only) VPS_PDC_UTC_BYTE_8[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x8D VDP_VPS_PDC_UTC_9 (read only) VPS_PDC_UTC_BYTE_9[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x8E VDP_VPS_PDC_UTC_10 (read only) VPS_PDC_UTC_BYTE_10[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x8F VDP_VPS_PDC_UTC_11 (read only) VPS_PDC_UTC_BYTE_11[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x90 VDP_VPS_PDC_UTC_12 (read only) VPS_PDC_UTC_BYTE_12[7:0] x x x x x x x x Decoded VPS/PDC/UTC data 0x92 VDP_VITC_DATA_0 (read only) VITC_DATA_0[7:0] x x x x x x x x Decoded VITC data 0x93 VDP_VITC_DATA_1 (read only) VITC_DATA_1[7:0] x x x x x x x x Decoded VITC data 0x94 VDP_VITC_DATA_2 (read only) VITC_DATA_2[7:0] x x x x x x x x Decoded VITC data 0x95 VDP_VITC_DATA_3 (read only) VITC_DATA_3[7:0] x x x x x x x x Decoded VITC data 0x96 VDP_VITC_DATA_4 (read only) VITC_DATA_4[7:0] x x x x x x x x Decoded VITC data 0x97 VDP_VITC_DATA_5 (read only) VITC_DATA_5[7:0] x x x x x x x x Decoded VITC data 0x98 VDP_VITC_DATA_6 (read only) VITC_DATA_6[7:0] x x x x x x x x Decoded VITC data 0x99 VDP_VITC_DATA_7 (read only) VITC_DATA_7[7:0] x x x x x x x x Decoded VITC data 0x9A VDP_VITC_DATA_8 (read only) VITC_DATA_8[7:0] x x x x x x x x Decoded VITC data 0x9B VDP_VITC_CALC_CRC (read only) VITC_CRC[7:0] x x x x x x x x Decoded VITC CRC data 0x9C VDP_OUTPUT_SEL Reserved 0 0 0 0 WSS_CGMS_CB_CHANGE 0 Disable content-based updating of CGMS and WSS data The available bit shows the availability of data only when its content has changed 1 Enable content-based updating of CGMS and WSS data GS_VPS_PDC_UTC_CB_CHANGE 0 Disable content-based updating of Gemstar, VPS, PDC, and UTC data 1 Enable content-based updating of Gemstar, VPS, PDC, and UTC data I2C_GS_VPS_PDC_UTC[1:0] 0 0 Gemstar_1×/Gemstar_2× Standard expected to be decoded 0 1 VPS 1 0 PDC 1 1 UTC 1 x indicates a bit that keeps the last written value. 2 Shading indicates default values. |
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