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ADV7180WBSTZ Datasheet(PDF) 106 Page - Analog Devices

Part # ADV7180WBSTZ
Description  10-Bit, 4횞 Oversampling SDTV Video Decoder
PDF  120 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7180WBSTZ Datasheet(HTML) 106 Page - Analog Devices

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ADV7180
Data Sheet
Rev. G | Page 106 of 120
I2C PROGRAMMING EXAMPLES
64-LEAD LQFP
Mode 1 CVBS Input (Composite Video on AIN2)
All standards are supported through autodetect, 8-bit, 4:2:2 ITU-R BT.656 output on P15 to P8 for the 64-lead LQFP.
Table 109. Mode 1 CVBS Input
Register Address (Hex)
Register Value (Hex)
Notes
00
01
INSEL = CVBS in on AIN2
04
57
Enable SFL
17
41
Select SH1
31
02
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
3D
A2
MWE enable manual window, color kill threshold to 2
3E
6A
BLM optimization
3F
A0
BGB optimization
0E
80
Hidden space
55
81
ADC configuration
0E
00
User space
Mode 2 S-Video Input (Y on AIN3 and C on AIN6)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8 for the 64-lead LQFP.
Table 110. Mode 2 S-Video Input
Register Address (Hex)
Register Value (Hex)
Notes
00
08
INSEL = Y/C, Y = AIN3, C = AIN6
04
57
Enable SFL
31
02
Clear NEWAVMODE, SAV/EAV to suit ADV video encoders
3D
A2
MWE enable manual window, color kill threshold to 2
3E
6A
BLM optimization
3F
A0
BGB optimization
58
04
Mandatory write; this must be performed for correct operation
0E
80
Hidden space
55
81
ADC configuration
0E
00
User space
Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN4, and Pb on AIN5)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8 for the 64-lead LQFP.
Table 111. Mode 3 YPrPb Input
Register Address (Hex)
Register Value (Hex)
Notes
00
09
INSEL = YPrPb, Y = AIN1, Pr = AIN4, Pb = AIN5
31
02
Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders
3D
A2
MWE enable manual window
3E
6A
BLM optimization
3F
A0
ADI recommended
0E
80
Hidden space
55
81
ADC configuration
0E
00
User space



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