XRT72L13 datasheet(134/370 Pages) EXAR

134 / 370 page

XRT72L13

MULTIPLEXER/FRAMER IC

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PRELIMINARY

REV. 1.0.6

122

This "Read-Only" bit-field indicates whether or not the

"FEAC Message Transmission Complete" interrupt

has occurred since the last read of this register. This

interrupt will occur once the Transmit FEAC Proces-

sor has finished its 10th transmission of the 16 bit

FEAC Message (6 bit FEAC Code word + 10 framing

bits). The purpose of this interrupt is to let the local

µP know that the Transmit FEAC Processor has com-

pleted its transmission of its latest FEAC Message

and is now ready to transmit another FEAC Message.

If this bit-field is "0", then the "FEAC Message Trans-

mission Complete" interrupt has NOT occurred since

the last read of this register.

If this bit-field is "1", then the "FEAC Message Trans-

mission Complete" interrupt has occurred since the

last read of this register.

NOTE: For more information on the Transmit FEAC Proces-

sor, please see Section _.

Bit 2 - TxFEAC Enable

This "Read/Write" bit-field allows the user to enable

or disable the Transmit FEAC Processor. The Trans-

mit FEAC Processor will NOT function until it has

been enabled.

Writing a "0" to this bit-field disables the Transmit

FEAC Processor. Writing a "1" to this bit-field en-

ables the Transmit FEAC Processor.

Bit 1 - TxFEAC Go

This bit-field allows the user to invoke the "Transmit

FEAC Message" command. Once this command has

been invoked, the Transmit FEAC Processor will do

the following:

• Encapsulate the 6 bit FEAC code word, from the Tx

DS3 FEAC Register (Address = 0x1D) into a 16 bit

FEAC Message

• Serially transmit this 16-bit FEAC Message to the

far-end receiver via the "outbound" DS3 data-

stream, 10 consecutive times.

NOTE: For more information on the Transmit FEAC Proces-

sor, please see Section _.

Bit 0 - TxFEAC Busy

This "Read-Only" bit-field allows the local µP to "poll"

and determine if the Transmit FEAC Processor has

completed its 10th transmission of the 16-bit FEAC

Message. This bit-field will contain a "1", if the Trans-

mit FEAC Processor is still transmitting the FEAC

Message. This bit-field will toggle to "0", once the

Transmit FEAC Processor has completed its 10th

transmission of the FEAC Message.

NOTE: For more information on the Transmit FEAC Proces-

sor, please see Section _.

2.3.2.47 TxDS3 FEAC Register

)

This register contains a six (6) bit "read/write" field

that allows the user to write in the six-bit FEAC code

word, that he/she wishes to transmit to the "Far End

Receive FEAC Processor", via the outgoing DS3 data

stream. The Transmit FEAC Processor will encapsu-

late this six-bit code into a 16-bit FEAC message, and

will proceed to transmit this message to the "Far End

Receiver" via the FEAC bit-field within each out-going

DS3 frame.

NOTE: For more information on the operation of the Trans-

mit FEAC Processor, please see Section _.

2.3.2.48 TxDS3 LAPD Configuration Register )

Bit 3 - Auto Retransmit

This "Read/Write" bit-field allows the user to config-

ure the LAPD Transmitter to either transmit the LAPD

TX DS3 FEAC REGISER (ADDRESS = 0X32)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

TxFEAC[5:0]

Not Used

R/WR/W

111

110

TXDS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

Auto

Retransmit

Not Used

TxLAPD Msg

Length

TxLAPD

Enable

R/WR/W

R/W

001

000

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