XRT72L13 datasheet(196/370 Pages) EXAR

196 / 370 page

XRT72L13

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

REV. P1.0.6

PRELIMINARY

184

address of the "burst access" has now been

selected.

NOTE: The ALE_AS input pin should remain "low" for the

remainder of this "Burst I/O Access" operation.

A.5

Next, the µC/µP should indicate that this cur-

rent bus cycle is a "Write" operation by keeping

the Rd_DS pin "high" and toggling the WR_RW

(Write Strobe) pin "low". This action also

enables the "bi-directional" data bus input driv-

ers of the Framer device.

A.6

The µC/µP places the byte (or word) that it

intends to write into the "target" register on the

"bi-directional data" bus, D[7:0].

A.7

After waiting the appropriate amount of time, for

the data (on the bi-directional data bus) to set-

tle, the µC/µP should toggle the WR_RW (Write

Strobe) input pin "high". This action accom-

plishes two things.

a. It latches the contents of the bi-directional data

bus into the XRT72L13 DS3 Framer Microproces-

sor Interface Block.

b. It terminates the write cycle.

Figure 53 presents a timing diagram which illustrates

the behavior of the Microprocessor Interface signals,

during the "initial" write operation within a Burst Ac-

cess, for an "Intel-type" µC/µP.

At the completion of this initial write cycle, the µC/µP

has written a byte or word into the first register or

buffer location (within the XRT72L13 DS3 Framer) for

this particular burst access operation. In order to il-

lustrate this point, the byte (or word) of data, that is

being written in Figure 53 has been labeled "Data to

be Written (Offset = 0x00)".

3.2.2.2.1.2.2

The Subsequent Write Operations

The procedure that the µC/µP must use to perform

the remaining write cycles, within this burst access

operation, is presented below.

B.0

Execute each subsequent write cycle, as

described in steps B.1 through B.3.

B.1

Without toggling the ALE_AS input pin (e.g.,

keeping it "low"); apply the value of the next

byte or word (to be written into the Framer) to

the bi-directional data bus pins, D[7:0].

FIGURE 53. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE "INITIAL" WRITE OPERATION

OF A

BURST CYCLE (INTEL-TYPE PROCESSOR)

ALE_AS

A[8:0]

CS*

D[7:0]

WRB_RW

Data to be Written (Offset = 0x00)

Address of “Initial” Target Register (Offset = 0x00)

RdB_DS

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