XRT72L13 datasheet(210/370 Pages) EXAR

210 / 370 page

XRT72L13

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

REV. P1.0.6

PRELIMINARY

198

Bits 6 thru 0 - RxDS2 AIS Channel [6:0]

These seven (7) “Read/Write” bit-fields permits the

user to specify which “inbound” DS2 channel (which

is demultiplexed from the inbound DS3 channel) will

carry an AIS (All Ones) pattern.

For example, setting “Bit 5” (within this register) to “1”

configures the XRT72L13 M13 device to overwrite the

contents of the de-multiplexed DS2 channel (corre-

sponding to channel 5) with the AIS (All Ones) pat-

tern.

Setting “Bit 5” to “0” configures the “Receive” DS2

Channel 5 to carry normal traffic (as de-multiplexed

from the inbound DS3 data stream).

3.3.2.13 DS3 Test Register

Bit 6 - Rx Payload Clock Enable

This “Read/Write” bit-field permits the user to config-

ure the “Receive Payload Data Output Interface” (of

the XRT72L13 M13 device) to generate either (a) a

gapped-serial clock signal or (b) an ungapped-serial

clock, along with an “RxOHInd” output signal.

Setting this bit-field to “0” configures the XRT72L13 to

generate an ungapped (44.736MHz) clock sjgnal via

the “RxClk” output pin, and to pulse the “RxOHInd”

output pin, coincident with an Overhead bit being out-

put via the “RxSer” output pin.

Setting this bit-field to “1” configures the XRT72L13 to

generate a gapped clock signal (e.g., a clock edge for

each payload bit) via the “RxOHInd” output pin.

NOTE: This feature is only applicable if the XRT72L13 has

been configured to operate in the “DS3 Clear Channel

Framer” Mode.

Bit 5 - Tx Payload Clock Enable

This “Read/Write” bit-field permits the user to config-

ure the “Transmit Payload Data Input Interface” (or

the XRT72L13 M13 device) to generate either (a) a

gapped-serial clock signal or (b) an ungapped-serial

clock, along with the “TxOHInd” output signal.

Setting this bit-field to “0” configurese the XRT72L13

to accept an ungapped clock (44.736MHz) signal via

the “TxInClk” input pin (or to output an ungapped

clock signal via the “RxOutClk” output pin). Further,

in this mode, the XRT72L13 will pulse the “TxOHInd”

output pin one bit period prior to the processing of an

overhead bit.

Setting this bit-field to “1” configures the XRT72L13 to

generate a gapped clock signal (e.g., a clock edge for

each payload bit) via the “TxOHInd” output pin.

NOTE: This feature is only applicable if the XRT72L13 has

been configured to operate in the “DS3 Clear Channel

Framer” Mode.

Bit 4 - Rx PRBS Lock Indicator

This “Read-Only” bit-field indicates whether or not the

“PRBS Checker/Receiver has acquired “PRBS Lock”

with the payload portion of the “inbound” DS3 data

stream.

M23 RX DS2 AIS REGISTER (ADDRESS = 0X0B)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

RxDS2 AIS

Channel 6

RxDS2 AIS

Channel 5

RxDS2 AIS

Channel 4

RxDS2 AIS

Channel 3

RxDS2 AIS

Channel 2

RxDS2 AIS

Channel 1

RxDS2 AIS

Channel 0

R/O

R/W

000

DS3 TEST REGISTER (ADDRESS = 0X0C)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

Rx Payload

Clock

Enable

Tx Payload

Clock

Enable

Rx PRBS

Lock

Indicator

Rx PRBS

Enable

Tx PRBS

Enable

Rx DS3

Bypass

Tx DS3

Bypass

R/O

R/W

R/O

R/W

000

XRT72L13 Datasheet(PDF) 210 Page - Exar Corporation

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