XRT72L13 datasheet(111/370 Pages) EXAR

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13

PRELIMINARY

REV. 1.0.6

Bit 0 - Flag Present

This "Read-Only" bit-field indicates whether or not the

LAPD Receiver has detected the occurrence of the

Flag Sequence byte (0x7E). A "0" in this bit-field indi-

cates that the LAPD Receiver does not detect the oc-

currence of the Flag Sequence byte. A "1" in this bit-

field indicates that the LAPD Receiver does detect

the occurrence of the Flag Sequence byte.

NOTE: For more information on the LAPD Receiver, please

see Section _.

2.3.2.24 M12 DS2 # 1 Configuration Register)

Bit 7 - Reserved

This bit-field must be set to “0”, in order for the

XRT72L13 M13 device to function properly.

Bit 6 - Reserved

This bit-field must be set to “0” in order for the

XRT72L13 M13 device to function properly.

Bit 5 - M12 Bypass

This “Read/Write” bit field permits the user to bypass

M12 Multiplexer/De-Multiplexer # 1. By doing this the

following will happen.

In the Transmit Direction

• The XRT72L13 M13 device will accept a DS2 clock

signal (6.312MHz) via the TxDS1Clk3 input pin.

• The XRT72L13 M13 device will accept a DS2 sig-

nal via the TxDS1Data_3 input pin

In the Receive Direction

• The XRT72L13 M13 device will output a DS2 clock

signal (6.312MHz) via the RxDS1Clk3 output pin.

• XRT72L13 M13 device will output the contents of

DS2 Channel # 1 via the RxDS1Data3 output pin.

Setting this bit-field to “1” configures M12 MUX # 1

and M12 DEMUX # 1 to be bypassed.

Setting this bit-field to “0” enables M12 MUX # 1 and

M12 DEMUX # 1.

Bit 4 - M12 G.747

This “Read/Write” bit-field permits the user to config-

ure M12 MUX # 1 and DEMUX # 1 to support either a

DS2 signal or an ITU-T G.747 signal.

Setting this bit-field to “0” configures M12 # 1 to sup-

port DS2. In this mode, the M12 MUX will accept four

DS1 signals (via TxDS1Data0 thru TXDS1Data3) and

will muitiplex these signals into a DS2 signal. Like-

wise, the M12 DEMUX will accept an incoming DS2

signal (from the M23 DEMUX) and will de-multiplex

this signal into 4 DS1 signals. These four DS1 sig-

nals will be output via the “RxDS1Data0” thru

“RxDS1Data3” output pins.

Setting this bit-field to “1” configures M12 # 1 to

support ITU-T G.747. In this mode, the M12 MUX will

accept 3 E1 signals (via TxDS1Data0 thru

TxDS1Data2) and will multiplex these signals into an

ITU-T G.747 signal. Likewise, the M12 DEMUX will

accept an incoming ITU-T G.747 signal (from the

M23 DEMUX) and will de-multiplexe this signal into 3

E1 signals. These three E1 signals will output via the

“RxDS1Data0” thru “RxDS1Data2” output pins.

Bit 3 - M12G.747 Reserved

Bit 2 - M12 FERF

This “Read/Write” bit-field permits the user to force

M12 MUX # 1 to transmit a “FERF” (Far-End-Receive

Failure) indicator to the M23 MUX (and in turn to the

remote terminal equipment).

Setting this bit-field to “1” configures the M12 MUX to

set the “X-bits” (within the “outbound” DS2 data

stream) to “0”. This signaling will be interpreted (by

the remote terminal equipment) as a FERF indicator.

Settiing this bit-field to “0” configures the M12 MUX to

set the “X-bits” (within the “outbound” DS2 data

stream) to “1”. This signaling will be interpreted (by

the remote terminal equipment) as an indication of no

FERF.

Bits 1 and 0 M12 LB Code[1:0]

M12 DS2 # 1 CONFIGURATION REGISTER (ADDRESS = 0X1A)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Reserved

M12

Bypass

M12

G.747

M12

G.747 Res

M12 FERF

M12LBCode[1:0]

R/W

0000

111

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