DP8344 datasheet(164/184 Pages) NSC

164 / 184 page

60 Reference Section (Continued)

621 Bit Index

(Continued)

An alphabetical listing of all statuscontrol bits in the CPU-addressable special function registers with a brief summary of

function Detailed definitions are provided in Section 623 Bit Definition Tables

Bit

Name

Location

Function

TFE

ransmit FIFO Empty

NCF

Transmitter Status

TFF

ransmit FIFO Full

TSR

Transmitter Status

TIN

ransmitter INvert

TMR

Transmitter Control

TLD

imer LoaD

ACR

Timer

TM7–0

iMer

TRL

7–0

Timer

TM15 – 8

iMer

TRH

7–0

Timer

TMC

iMer Clock select

ACR

Timer

ime Out flag

CCR

Timer

TRES

ransceiver RESet

TMR

Transceiver Control

TST

imer StarT

ACR

Timer

VoVerflow

CCR

Arithmetic Flag

ero

CCR

Arithmetic Flag

622 Register Description

A list of all CPU-addressable special function registers in

alphabetical order

The Remote Interface Configuration register RIC

which is

addressable only by the remote system is not included See

Section 63 Remote Interface Reference for details of the

function of this register

Each register is listed together with its address the type of

access available and a functional description of each bit

Further details on each bit can be found in Section 623 Bit

Definition Tables

ACR

AUXILIARY CONTROL REGISTER

Main R3 readwrite

TST

TLD

TMC

BIC

rsv

COD

LOR

GIE

rsv

state is undefined at all times

TST

Timer StarT

When high the timer is enabled

and will count down from it’s current value

When low timer is disabled Timer is stopped by

writinga0to TST

TLD

Timer LoaD

When high generates timer load

pulse Cleared when load complete

TMC

TiMer Clock select

Selects timer clock fre-

quency Should not be written when

TST

high Can be written at same time as TST and

TLD

TMC

Timer Clock

(CPU-CLK)16

(CPU-CLK)2

BIC

Bi-directional Interrupt Control

Controls di-

rection of BIRQ

BIC

BIRQ

Input

Output

COD

Clock Out Disable

When high CLK-OUT out-

put is at TRI-STATE

LOR

Lock Out Remote

When high a remote sys-

tem is prevented from accessing the BCP

GIE

Global Interrupt Enable

When low disables

all maskable interrupts When high works with

IM4–0 to enable maskable interrupts

4TR

4 T-state Read

When high READ strobe tim-

ing is changed to allow more time between the

TRI-STATE of the AD lines by the BCP and the

falling of the READ strobe All data memory reads

take four T-states when this bit is set See Sec-

tion 222 for more information

164

DP8344 Datasheet(PDF) 164 Page - National Semiconductor (TI)

DP8344 Datasheet(HTML) 164 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL