DP8344 datasheet(166/184 Pages) NSC

166 / 184 page

60 Reference Section (Continued)

DCR

DEVICE CONTROL REGISTER

Alternate R0 readwrite

76543210

CCS

TCS1 TCS0

IW1

IW0

DW2

DW1

DW0

CCS

CPU Clock Select

Selects CPU clock fre-

quency OCLK represents the frequency of the

on-chip oscillator or the externally applied clock

on input X1

CCS

CPU CLK

OCLK

OCLK2

TCS10

Transceiver Clock Select

Selects trans-

ceiver clock TCLK frequency

OCLK represents the frequency of the on-chip

oscillator or the externally applied clock on in-

put X1 X-TCLK is the external transceiver

clock input

TCS10

TCLK

0 0

OCLK

0 1

OCLK2

1 0

OCLK4

1 1

X-TCLK

IW10

Instruction memory Wait-state select

Selects from 0 to 3 wait states for accessing

instruction memory

DW2–0

Data memory Wait-state select

Selects

from 0 to 7 wait states for accessing data mem-

ory

DATA STACK

Main R31 readwrite

76543210

DS7

DS6

DS5

DS4

DS3

DS2

DS1

DS0

DS7–0

Data Stack

Data stack inputoutput port

Stack is 16 bytes deep Further information

Section 2118 Stack Registers

rsv

state is undefined at all times

166

DP8344 Datasheet(PDF) 166 Page - National Semiconductor (TI)

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