DP8344 datasheet(165/184 Pages) NSC

165 / 184 page

60 Reference Section (Continued)

ATR

AUXILIARY TRANSCEIVER REGISTER

Alternate R2 readwrite

76543210

AT7

AT6

AT5

AT4

AT3

AT2

AT1

AT0

AT7–0

Auxiliary Transceiver

In 5250 protocol

modes bits 2 – 0 define the receive station ad-

dress and bits 7 – 3 control the amount of time

TX-ACT stays asserted after the last fill bit

In 8-bit protocol modes bits 7 – 0 define the re-

ceive station address

For further information see Section 30 Trans-

ceiver

ATR 7 – 3

TX-ACT Hold Time (ms)

(if TCLK e 8 MHz)

00000

00001

0 5

00010

1 0

00011

1 5

11111

155

CCR

CONDITION CODE REGISTER

Main R0 bits 0 – 3 5 – 7 readwrite bit 4 read only

765

3210

BIRQ

Time Out flag

Set high when timer counts to

zero Cleared by writinga1to this location or by

stopping timer (by writinga0to TST )

Remote Read

Set on the trailing edge of a

REM-RD pulse if RAE is asserted and RIC is

pointing to Data Memory Cleared by writing a 1

to this location

Remote Write

Set on the trailing edge of a

REM-WR pulse if RAE is asserted and RIC is

pointing to Data Memory Cleared by writing a 1

to this location

BIRQ

Bi-directional Interrupt ReQuest

Read

only

Reflects the logic level of the Bi-directional

interrupt pin BIRQ Updated at the beginning of

each instruction cycle

Negative

A high level indicates a negative

result generated by an arithmetic logical or shift

instruction

oVerflow

A high level indicates an overflow

condition generated by an arithmetic instruction

Carry

A high level indicates a carry or borrow

generated by an arithmetic instruction During a

shiftrotate operation the state of the last bit shift-

ed out appears in this location

Zero

A high level indicates a zero result gen-

erated by an arithmetic logical or shift instruction

Further information Section 221 ALU Section

223 Interrupts

165

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