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DP8344 Datasheet(PDF) 168 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 168 Page - National Semiconductor (TI) |
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168 / 184 page ![]() 60 Reference Section (Continued) IBR INTERRUPT BASE REGISTER Alternate R1 readwrite 76543210 IV15 IV14 IV13 IV12 IV11 IV10 IV9 IV8 IV15 – 8 Interrupt Vector High byte of interrupt and trap vectors Further information Section 223 Interrupts Interrupt Vector IBR 0 0 vector address 15 8 5 0 The interrupt vector is obtained by concatenating IBR with the vector address Interrupt Vector Address Priority NMI 011100 Receiver 000100 1 high Transmitter 001000 2 u Line Turn Around 001100 3 Bi-directional 010000 4 v Timer 010100 5 low ICR INTERRUPT CONTROL REGISTER Main R2 readwrite 76543210 RIS1 RIS0 rsv IM4 IM3 IM2 IM1 IM0 rsv state is undefined at all times RIS10 Receiver Interrupt Select Defines the source of the Receiver Interrupt RIS10 Interrupt Source 0 0 RFF a RE 0 1 DAV a RE 1 0 (unused) 11 RA ‘‘a’’ indicates logical ‘‘or’’ Further information Section 323 Transceiver In- terrupts IM4–0 Interrupt Masks Each bit when set high masks an interrupt IM3 functions as an interrupt mask only if BIRQ is defined as an input When BIRQ is defined as an output IM3 controls the state of BIRQ IM4 – 0 Interrupt 00000 No Mask XXXX1 Receiver XXX1X Transmitter XX1XX Line Turn-Around X1XXX Bi-Directional 1XXXX Timer Further information Section 223 Interrupts 168 |
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