DP8344 datasheet(172/184 Pages) NSC

172 / 184 page

60 Reference Section (Continued)

TRL

TIMER REGISTERLOW

Main R28 readwrite

76543210

TM7

TM6

TM5

TM4

TM3

TM2

TM1

TM0

TM7–0

TiMer

Inputoutput port of low byte of timer

Further information Section 2114 Timer Regis-

ters

TSR

TRANSCEIVER STATUS REGISTER

Alternate R5 read only

TFF

DAV

RF10

RF9

RF8

TFF

Transmit FIFO Full

Set high when the trans-

mit FIFO is full

RTR

must not be written to

when TFF is high

Transmitter Active

Reflects the state of TX-

ACT indicating that data is being transmitted

Unlike TX-ACT however TA is not disabled by

LOOP

Receiver Error

Set high when a receiver er-

ror is detected Cleared by reading ECR or by

asserting TRES

Receiver Active

Set high when a valid start-

ing sequence is received Cleared when either

an end of message or an error is detected In

5250 modes

RA is cleared at the same time

as LA

DAV

Data AVailable

Set high when valid data is

available in RTR and TSR

Cleared by read-

ing RTR

or when an error is detected

RF10 – 8

Receive FIFO

RF10 – 8 and RTF7 – 0 re-

flect the state of the top word of the receive

FIFO

Further information Section 30 Transceiver

172

DP8344 Datasheet(PDF) 172 Page - National Semiconductor (TI)

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