DP8344 datasheet(174/184 Pages) NSC

174 / 184 page

60 Reference Section (Continued)

623 Bit Definition Tables

(Continued)

The following tables describe the location and function of all control and status bits in the various BCP addressable special

function registers The Remote Interface Configuration register

RIC

which is addressable only by a remote processor is not

included

6231 Processor

(Continued)

Bit

Name

Location

Reset State

Function

Interrupt

IV15 – 8

nterrupt Vector

IBR 7–0

0000 0000

High byte of interrupt and trap vectors

Control

The interrupt vector is obtained by concatenating IBR with

the vector address

(Continued)

Interrupt

Vector Address

NMI

011100

Receiver

000100

Transmitter

001000

Line Turn Around

001100

Bi-Directional

010000

Timer

010100

Interrupt Vector

IBR

vector address

RIS10

eceiver Interrupt ICR 76

Defines the source of the receiver interrupt

elect

RIS10 Interrupt Source

0 0

RFF a RE

0 1

DAV a RE

1 0

(unused)

Address

ASP3 – 0

ddress Stack

ISP 7–4

0000

Address stack pointer Writing to this location changes the

value of the pointer

and

ointer

Data

Stacks

DSP3 – 0 Data Stack

ISP 3–0

0000

Data stack pointer Writing to this location changes the value

of the pointer

ointer

DS7–0

ata Stack

DS 7–0

XXXX XXXX

Data Stack InputOutput port Stack is 16 bytes deep

Arithmetic

arry

CCR 1

A high level indicates a carry or borrow generated by an

arithmetic instruction During a shiftrotate operation the

Flags

state of the last bit shifted out appears in this location

egative

CCR 3

A high level indicates a negative result generated by an

arithmetic logical or shift instruction

VoVerflow

CCR 2

A high level indicates an overflow condition generated by an

arithmetic instruction

ero

CCR 0

A high level indicates a zero result generated by an

arithmetic logical or shift instruction

174

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