DP8344 datasheet(178/184 Pages) NSC

178 / 184 page

60 Reference Section (Continued)

623 Bit Definition Tables

(Continued)

6232 Transceiver

(Continued)

Table includes control and status bits only It does not include definitions of bit fields provided for the formatting (de-formatting)

data frames For further information see the Transceiver section

Bit

Name

Location Reset State

Function

Receiver

IES

nvalid Ending

ECR 2

Set when the first mini-code violation is not correct during a

3270 3299 or 8-bit ending sequence Cleared by reading

Error Codes

equence

ECR or asserting TRES

LMBT

oss of Mid-Bit

ECR 1

Set when the expected Manchester Code mid-bit transition

does not occur within the allowed window Cleared by reading

ransition

ECR or by asserting TRES

OVF

receiver OVerFlow ECR 4

Set when the receiver has processed 3 words and another

complete frame is received before the FIFO is read by the

CPU Cleared by reading ECR or asserting TRES

PAR

ity error

ECR 3

Set when bad (odd) overall word parity is detected in any

receive frame Cleared by reading ECR or asserting

TRES

RDIS

eceiver DISabled ECR 0

Set when transmitter is activated by writing to RTR while

receiver is still active without RPEN first being asserted

while active

Cleared by reading ECR or asserting TRES

63 REMOTE INTERFACE CONFIGURATION REGISTER

This register can be accessed only by the remote system

To do this CMD and RAE must be asserted and the LOR

bit in the ACR register must be low

BIS

STRT

MS1

MS0

RIC

BIS

idirectional Interrupt Status

Mirrors the state

of IM3 ( ICR bit 3) enabling the remote system to

poll and determine the status of the BIRQ IO

When BIRQ is an output the remote system can

change the state of this output by writing a one to

BIS This can be used as an interrupt acknowl-

edge whenever BIRQ is used as a remote inter-

rupt For complete information on the relationship

between BIS IM3 and BIRQ refer to Section 223

Interrupts

ingle-Step

Writing a 1 with STRT low the BCP

will single-step by executing the current instruction

and advancing the PC On power upreset this bit

is low

ast Write

When high with LW low selects fast

write mode for the buffered interface When low

selects slow write mode On power upreset this

bit is low (LW will also be low so buffered write

mode is selected)

atched Read

When high selects latched read

mode when low selects buffered read mode On

power upreset this bit is low (Buffered read mode

is selected)

atched Write

When high selects latched write

mode when low selects buffered write mode On

power upreset this bit is low (FW will also be low

so slow buffered write mode is selected)

STRT

aRT

The remote system can start and stop

the BCP using this bit On power-upreset this bit is

low (BCP stopped) When set the BCP begins exe-

cuting at the current Program Counter address

When cleared the BCP finishes executing the cur-

rent instruction then halts to an idle mode

In some applications where there is no remote

system or the remote system is not an intelligent

device it may be desirable to have the BCP power-

upreset running rather than stopped at address

0000H This can be accomplished by asserting

REM-RD REM-WR and RESET with RAE de-as-

serted (Refer to Electrical Specification Section

for the timing information needed to start the BCP

in stand alone mode)

MS10

emory Select 10

These two bits determine

what the remote system is accessing in the BCP

system according to the following table

MS1

MS0

Selected Function

Data Memory

Instruction Memory

Program Counter (Low Byte)

Program Counter (High Byte)

The BCP must be idle for the remote system to

readwrite Instruction memory or the Program

Counter

All remote accesses are treated the same (inde-

pendent of where the access is directed using MS0

and MS1) as defined by the configuration bits LW

LR FW

If the remote system and the BCP request data

memory access simultaneously the BCP will win

first access If the locks ( LOR LOCK) are not set

the remote system and BCP will alternate access

cycles thereafter

On power-upreset MS10 points to instruction

memory

Power-upReset state of RIC 7-0

l000 000l

178

DP8344 Datasheet(PDF) 178 Page - National Semiconductor (TI)

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