DP8344 datasheet(182/184 Pages) NSC

182 / 184 page

60 Reference Section (Continued)

banked registers

Two or more sets of CPU registers that

occupy the same register space but only one of which is

accessible at a time

barrel shifter

Dedicated hardware for shifting and rotat-

ing

BCP

An abbreviation for Biphase Communications Proc-

essor the National Semiconductor DP8344

biphase

In this communications signal encoding tech-

nique the data is divided into discrete bit time intervals de-

noted by a transition in the center of the bit time This tech-

nique combines the clock and data information into one

transmission In 3270 and 3299 protocols a mid-bit tran-

sition from low to high represents a bi-phase 1 and a mid-

bit

transition from high to low represents a bi-phase 0 For

the 5250 protocol the definition of biphase logic levels is

reversed Biphase encoding is also called Manchester II

encoding

BIRQ

The Bidirectional Interrupt ReQuest Without any

other notation BIRQ will refer to the BIRQ interrupt itself

BIRQ with a bar on top of it (BIRQ) is used where the pin is

referenced BIRQ in brackets ( BIRQ )isbit4inthe

CCR register

coax

(1) RG-62AU 93X coaxial cable that is used in

3270

protocol systems (2) Sometimes this term is used to

refer to the 3270 protocol itself

code violation

A violation of the bi-phase encoding for-

mat that is part of the start sequence In 3270 3299 and

the general purpose 8-bit mode the code violation is 1

bit times low and then 1

bit times high In the 5250 proto-

col the signal levels are reversed

communications protocol

A set of rules which defines

the physical electrical control and formatting specifica-

tions required to successfully transfer data between two

systems

context switch

Switching between two theoretically inde-

pendent functions that should not affect each other except

under specified circumstances

controller

The master device that initiates all communica-

tion to the slave device and controls the manner in which

the slave presents the information It acts as the interface

both physically and logically between the slave terminals

and printers and a host processor

CPU-CLK

The clock that the operation of the BCP’s CPU

is synchronized to The period of this clock which defines

T-state

boundaries is either that of OCLK or one-half of

OCLK

depending on the configuration of the BCP The tim-

er clock is also derived from CPU-CLK

CUT

Control Unit Terminal A mode of the controller

where attached devices have limited intelligence and are

perceived to be hardware extensions of the controller The

controller

directs all printer screen and keyboard activity

DFT

Distributed Function Terminal A controller mode

that supports multiple logical terminals in the same device

The controller communicates in higher level commands via

data placed in the buffer The slave device has a greater

amount of intelligence than the CUT mode device and is

responsible for the terminal operation

direct coupled

The connection of the transceiver to the

transmission cable in a manner that does not isolate it from

DC voltages Contrast this with transformer coupled

dual port memory

A memory architecture that allows two

different processors to access the same memory range al-

ternately

ending sequence

A defined sequence of bits signifying

the end of a transmission In 3270 and 3299 it consists of a

bi-phase

0 followed by a low to high transition on the bit

time boundary and two mini-code violations

FIFO

A section of memory or as in the case of the BCP

transceiver a set of registers that are accessed in a First-In

First-Out method In other words the first data placed in the

FIFO by a write will be the first data removed by a read

fill bits

Fill bits are bi-phase 0’s used only in the 5250

protocol A minimum of three fill bits are required between

each frame of a multi-frame message This number may

be increased by the controller to approximately 243 per the

SetMode command There are always only three fill bits af-

ter the last frame of the transmission

general purpose 8-bit mode

A generic communications

mode similar to 3270 and 5250 frame formatting using 8-bit

serial data and bi-phase signal encoding The BCP sup-

ports both promiscuous and non-promiscuous modes

Harvard architecture

A computer architecture where the

instruction and data memory are organized into two inde-

pendent memory banks each with their own address and

data buses

hold time

The amount of time the line is driven at the end

of 5250 transmissions to suppress noise on the cabling sys-

tem

ICLK

The clock that identifies the start of each instruction

when it rises and indicates when the next instruction ad-

dress is valid when it falls

immediate addressing mode

An addressing method

where one operand the data for Move instructions and the

address for Jump instructions is contained in the instruction

itself

immediate-relative addressing mode

An addressing

method that adds an unsigned 8-bit immediate number to

the index register IZ to form the data memory address of an

operand

indexed addressing mode

An addressing method that

uses the contents of an index register as the data memory

address for one of the operands in an instruction

interrupt latency

The time from when an interrupt first

occurs until it begins executing at its interrupt vector

jitter

Timing variations for signals of different harmonic

content that move the edges of a transmitted signal in time

causing uncertainty in their decoding

jitter tolerance

The total amount of time an edge of a

transmitted bit may move and still have its data bit decoded

correctly

LIFO

A sequence of registers or memory locations that

are accessed in a Last-In First-Out method in other words

the last data written into the LIFO will be the first to be

removed by a read Also known as a stack

limited register set

In the BCP the first 16 register ad-

dress locations (R0 – R11 in both banks and R12 – R15) that

can be used in all instructions

182

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