DP8344 datasheet(181/184 Pages) NSC

181 / 184 page

60 Reference Section (Continued)

4TR in ACR

When a one is written to this bit all subse-

quent data memory read operations expand to 4 T-states

with an extra one-half T-state between the falling edge of

ALE and the falling edge of READ This eliminates bus con-

tention on data memory read operations After a BCP reset

or when a zero is written to this bit the DP8344B data mem-

ory read operations operate in 3 T-states

as in the

DP8344A in which this bit was unused (See Section 222

for more information)

6622 AAD Reset State

After a BCP reset the index registers and the A and AD

buses will be zero In the DP8344A their states were unde-

fined after a reset

6623 RIC

Each time instruction memory is selected via

RIC 10

(ie

RIC is set to XXXX XX01 binary) the next read (or

write) of instruction memory by a remote processor will al-

ways return (or update) the low order 8 bits of the 16 bit

instruction location pointed to by the program counter In

the DP8344A setting RIC had no affect on which instruc-

tion memory byte would next be fetched and an algorithm

had to be developed to determine this (See Section 412

for more information)

6624 Transceiver

When the Transceiver is reset DATA-OUT now goes into a

state equal to TIN Z ATA

which eliminates coincident

transitions on DATA-OUT and DATA-DLY with TX-ACT

(See Section 32 for more information

67 REPORT BUGS

671 History

The

DP8344

Data

Sheet

Reference

first

published

102987 (rev 36) listed a total of 13 bugs All these bugs

were corrected in the DP8344A released to production April

1989 Subsequent to this date an additional bug has been

reported This bug is present in all versions of the BCP

DP8344 DP8344A and DP8344B

For additional information regarding differences in function-

ality between the DP8344B and DP8344A see Section 66

672 LJMP LCALL Address Decode

The LJMP and LCALL instructions to the address range

Af00h through AF7Fh do not function correctly Both condi-

tional and unconditional LCALL or LJMP instructions to this

address range will not decode as LCALL or LJMP instruc-

tions Instead the address field will be incorrectly decoded

as the instruction Thus a LJMP or LCALL to an instruction

in the address range AF00h through AF7Fh will be decoded

as a RETF instruction

LJMP AF00

Example the instruction

AF00

will be decoded as

RETF 000

which is

Note that LJMP and LCALL to all other addresses work cor-

rectly

The LJMP or LCALL instruction should therefore not be

used to transfer program control to an instruction in the

range AF00h to AF7Fh

6721 Suggested Work-around

The simplest work-around is not to place any code neces-

sary for system operation in the affected address range

This can be accomplished by creating a section of ‘‘filler’’

code that will occupy the instruction address range AF00h

to AF7Fh As an example the ‘‘filler’’ section of code could

be as follows

FILLER

SECT X

Start of ‘‘filler’’ code section

REPEAT 128

Repeat the following

instruction 128 times

JMP $

Jump to self

ENDR

End of repeat block

END

The JMP $ instruction causes an infinite loop at that instruc-

tion Thus one would be able to determine if the program

inadvertently entered the ‘‘filler’’ section of code The re-

peat 128 instruction causes the section to occupy 128 bytes

of instruction memory which is the size of the affected ad-

dress range

Next by using the Linker in the DP8344 BCP Assembler

System one can specify that this ‘‘filler’’ section of code

must occupy instruction memory starting at address AF00h

by using the -L option For example the following com-

mands can be entered at the DOS command line to invoke

the Assembler and Linker (this assumes that the ‘‘filler’’

section is located in the file FILLERBCP)

NBCPASM FILLERBCP

NLINK -LFILLER

4AF00 FILLRBCO

This will prevent any other section of code from occupying

the range which the ‘‘filler’’ section of code is located in

Hence one would not have to be concerned about using

labels to specify the address in LJMP and LCALL instruc-

tion

68 GLOSSARY

3270

An IBM communication protocol originally devel-

oped for the 370 class mainframe that implements a star

topology using a single coax cable per slave device In this

master-slave protocol all communication is initiated by the

controller

(master) and responses are returned by the ter-

minal or other attached device (slave) The data is transmit-

ted using biphase encoding at a bit rate of 23587 MHz

3299

A communications protocol that is the 3270 proto-

col with an eight bit address frame added to the beginning

of each controller transmission between the start se-

quence

and the first coax word Currently IBM only uses

three bits of the address field which allows up to eight devic-

es to communicate with the controller through a multiplex-

5250

An IBM communications protocol originally devel-

oped for the Series 3 that became widely used on the Sys-

tem 343638 family of minicomputers and currently the

AS400 It uses a multidrop bus topology on twin-ax cable

This protocol is a master-slave type The data is transmitted

using bi-phase encoding at a bit rate of 1 MHz

accumulator

The implied source register of one operand

for some arithmetic operations In the BCP R8 in the cur-

rently enabled bank acts as the accumulator

ALU

The Arithmetic Logic Unit a component of the CPU

that performs all arithmetic (addition and subtraction) logi-

cal (AND OR XOR compare bit test and complement)

rotational and shifting operations

ALU flags

Bits that indicate the result of certain ALU func-

tions

181

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