DP8344 datasheet(180/184 Pages) NSC

180 / 184 page

60 Reference Section (Continued)

Scope are single PC expansion cards that can record de-

code and display activity on the 3270 coax and 5250 twinax

line respectively These devices also allow the play back of

the recorded controller information Capstone Technology

also supplies a line monitor The CT101C Network Analysis

Monitor (NAM) is a coax line monitor

These companies can be contacted at the following loca-

tions

Azure Technology Inc

38 Pond Street

Franklin Massachusettes 02038

(508) 520-3800

Capstone Technology

853 Brown Rd Suite 207

Fremont California 94539

(415) 438-3500

New Leaf Technology Ltd

24A High Street

Cobham

Surrey

KT113EB

ENGLAND

(0932) 66466

For technical assistance in using the DP8344B contact the

BCP Hot Line (817) 468-6676

TABLE 6-4 DP8344 Application Notes

App

Note No

Title

AN-623

Interfacing Memory to the DP8344B

AN-624

A Combined Coax-Twisted Pair 3270 Line

Interface for the DP8344 Biphase

Communications Processor

AN-516

Interfacing the DP8344 to Twinax

AN-504

DP8344 BCP Stand-Alone Soft-Load

System

AN-499

‘‘Interrupts’’-A Powerful Tool of the Biphase

Communications Processor

AN-625

JRMK Speeds Command Decoding

AN-627

DP8344 Remote Processor Interfacing

AN-626

DP8344 Timer Application

AN-641

MPA - A Multi-Protocol Terminal Emulation

Adapter Using the DP8344

AN-688

The DP8344 BCP Inverse Assembler

66 DP8344A AND DP8344B COMPATIBILITY GUIDE

The DP8344B is an enhanced version of the DP8344A ex-

hibiting improved switching performance and additional

functionality The device has been characterized in a num-

ber of applications and found to be a compatible replace-

ment for the DP8344A Differences between the DP8344A

and DP8344B are detailed in this section

661 Timing Changes to the CPU

Relative to the DP8344A the DP8344B incorporates a num-

ber of timing changes designed to improve the system inter-

face These timing changes are improvements in the timing

specifications and therefore should allow the DP8344B to

drop into existing DP8344A designs without any hardware

modifications

The DP8344A exhibits a small amount of contention be-

tween certain bus signals as detailed in the Device Specifi-

cations section of this data sheet The DP8344B interface

timing improvements are designed to reduce andor elimi-

nate this bus contention

70 ns Data Memory

At a 20 MHz CPU clock rate the DP8344B can support 70

ns static RAM for data memory with no wait states The

DP8344A was limited to 55 ns static RAM for data memo-

ry with no wait states (See Section 50 Device Specifica-

tions)

READ

The timing of the READ strobe has been improved to re-

duce bus contention during a data memory access There

is now more time between AD disabled and READ falling

as well as one-half T-state between READ rising and AD

enabled In addition a new 4 T-state read option has been

provided to eliminate bus contention (See Section 50 De-

vice Specifications for timing changes and 4 T-state

Read

later in this document for more information on the 4

T-state Read option)

The user can therefore choose between a fast read mode

(3 T-states) with a small amount of contention and a slow-

er read mode (4 T-states) with no contention

AAD Bus Timing

The timing of the A and AD buses has been changed to

eliminate bus contention during remote accesses of data

memory There is now a one-half T-state TRI-STATE zone

during the bus transfer from local to remote control and

vice versa (See Section 50 Device Specifications)

IWR

The timing of IWR has been changed such that IWR now

falls one T-state earlier This eliminates bus contention

during the start of soft loads (See Section 50 Device

Specifications)

IA Bus Softload Timing

The auto-increment of the IA bus address during soft

loads of instruction memory now occurs one T-state later

to maintain in-phase data and thereby eliminate bus con-

tention (See Seection 50 Device Specifications)

LCL

LCL is now removed when REM-RD is taken high on buff-

ered reads of RIC

the program counter and instruction

memory to eliminate bus contention in this mode (See

Section 50 Device Specifications)

RIC

The hold time on slow buffered writes to RIC and the

program counter has been improved (See Section 50 De-

vice Specifications)

‘‘Kick-start’’

The hold time on REM-WR and REM-RD to RESET to

‘‘kick-start’’ the CPU has been improved (See Section 50

Device Specifications)

662 Additional Functionality of the DP8344B

6621 4 T-state Read

To eliminate bus contention during memory accesses a

new optional read mode has been created controlled by

180

DP8344 Datasheet(PDF) 180 Page - National Semiconductor (TI)

DP8344 Datasheet(HTML) 180 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL