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DP8344 Datasheet(PDF) 183 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 183 Page - National Semiconductor (TI) |
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183 / 184 page ![]() 60 Reference Section (Continued) line hold The act of driving the transmission line during 5250 transmissions at the end of a message to allow the receivers to unsync This insures that the receivers will not see line noise as the start of another frame when the line floats line interface All the circuity between the BCP and the communications cable medium line reflection Energy from a transmission that is not ab- sorbed by a load impedance and can cause interference in that signal Manchester II encoding See bi-phase encoding mask (1) A mechanism that allows the program to specify whether interrupts will be accepted by the CPU (2) To dis- able the accepting of an interrupt by the CPU mid-bit In bi-phase encoding the transition in the center of a bit time mini-code violation A violation of the bi-phase encoding format that is part of the ending sequence in 3270 3299 and the general purpose 8-bit mode The mini-code viola- tion has no mid-bit transition being high for the entire bit time There is no mini-code violation in 5250 multidrop A communication method where all the slave devices are attached to the same cable and respond to controller commands and data only when their own ad- dress frame precedes the transmitted frame multi-frame message Several bytes of data together in the same uninterrupted message that have only one start sequence and one ending sequence multiplexer A device that receives 3299 protocol trans- missions from a controller strips off the address field and determines over which of eight ports to transmit the mes- sage in 3270 format The device then directs the response from the terminal back to the controller non-promiscuous A receiver mode that only enables a data available interrupt when the address frame of the mes- sage matches that previously specified The 5250 and gen- eral purpose 8-bit modes of the BCP support both pro- miscuous and non-promiscuous modes NRZ Non Return to Zero A data format that uses a high level to represent a data 1 and a low level to represent a data 0 The signal level does not return to a zero level in each bit time See also NRZI NRZI Non Return to Zero Inverted A data format similar to NRZ but with the signal levels reversed OCLK The external Oscillator CLocK connected to the BCP This frequency from a crystal or a clock cannot be changed by the BCP itself CPU-CLK is derived from OCLK in addition the transceiver can be configured so that TCLK is derived from OCLK parity A one bit code usually following data that makes the total number of 1’s in a data word odd or even including the parity bit itself It is included as an error checking mech- anism POLL A command issued by a controller to determine changes in terminal status such as keyboard activity or key- lock POLLACK (PACK) A command issued by a controller to indicate to the terminal that the controller has recognized the non-zero status response of the terminal to its POLL hence its full name pollacknowledge pop To remove data from a stack predistortion The initial voltage step in a Manchester encoded bit used to change frequency components of the signal to limit introducing jitter promiscuous A receiver mode that enables a data avail- able interrupt regardless of the contents of the transmission address frame The 5250 and general purpose 8-bit modes of the BCP support both promiscuous and non-pro- miscuous modes push To place data onto a stack quiesce pulse A bi-phase 1 bit that is placed at the be- ginning of a transmission to charge the cable in preparation for the transmission of data In addition the quiesce pulses are used as part of the identifying start sequence Typical- ly five quiesce pulses are placed there register addressing mode An addressing method that uses only operands contained in registers register-relative addressing mode An instruction ad- dressing mode that adds the unsigned 8-bit value in the current accumulator to any one of the index registers form- ing a data memory address for one of the instruction’s oper- ands remote access An access to dual port memory by a device other than the BCP repeater A device used to extend the communication dis- tance between a controller and a slave device by receiving the message and re-transmitting it RIAS The Remote Interface and Arbitration System that allows a remote processor and the BCP to share the same memory with arbitration of any conflict while the BCP is run- ning A remote processor may also stop and start the BCP as well as read and write the Program Counter soft-loadable A feature of a processor system that allows another processor to provide it with instructions and data stack See LIFO start sequence A unique arrangement of bits that begin each transmission to ensure proper frame alignment and synchronization Each transmission begins with five bi- phase encoded 1’s quiesce pulses a code violation and the sync bit of the first frame station address The identification number of a 5250 ter- minal or other slave device that will specify which device on a multidrop line a message is sent to sync bit A bi-phase 1 that is placed as the first bit of a frame T-state The period of CPU-CLK TCLK The Transceiver CLocK that runs both the transmit- ter and receiver at a frequency equal to eight times the re- quired serial data rate The clock can be obtained from a scaled OCLK or from X-TCLK time-out An interrupt that occurs when the timer reaches a count of zero transceiver The TRANSmitter used for sending mes- sages and the reCEIVER used for reading messages transformer coupled The isolation of the transceiver from the transmission cable through the use of a transform- er Contrast this with direct coupled trap A BCP instruction that forces a software interrupt 183 |
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