DP8344 datasheet(173/184 Pages) NSC

173 / 184 page

60 Reference Section (Continued)

623 Bit Definition Tables

The following tables describe the location and function of all control and status bits in the various BCP addressable special

function registers The Remote Interface Configuration register

RIC

which is addressable only by a remote processor is not

included

6231 Processor

Bit

Name

Location

Reset State

Function

Timing

CCS

PU Clock Select

DCR 7

Selects CPU clock frequency

Control

Where OCLK is the frequency of the on-chip oscillator or

the externally applied clock on input X1

DW2–0

ata memory

DCR 2–0

111

Selects from 0 to 7 wait states for accessing data memory

ait-state select

IW10

nstruction memory

DCR 43

Selects from 0 to 3 wait states for accessing instruction

memory

ait-state select

COD

lock Out Disable

ACR 2

When high CLK-OUT is at TRI-STATE

4TR

4 T-state Read

ACR 3

When high data memory reads take four T-states

Remote

LOR

ock Out Remote

ACR 1

When high a remote processor is prevented from accessing

the BCP or its memory

Interface

emote Read

CCR 6

Set on the trailing edge of a REM-RD pulse if RAE is

asserted and RIC is pointing to Data Memory Cleared by

writinga1to RR

emote Write

CCR 5

Set on the trailing edge of a REM-WR pulse if RAE is

asserted and RIC is pointing to Data Memory Cleared by

writinga1to RW

Interrupt

BIC

i-directional

ACR 4

Controls the direction of BIRQ

Control

nterrupt Control

BIRQ

i-directional

CCR 4

Read Only Reflects the logic level of the BIRQ input

Updated at the beginning of each instruction cycle

nterrupt ReQuest

GIE

lobal Interrupt

ACR 0

When low disables all maskable interrupts When high

works with IM4–0 to enable maskable interrupts

nable

IM4–0

nterrupt Mask

ICR 4–0

11111

Each bit when set high masks an interrupt

select

IM3 functions as an interrupt mask only when BIRQ is

defined as an input When BIRQ is defined as an output IM3

controls the state of BIRQ

CCS

CPU CLK

OCLK

OCLK2

BIC

BIRQ

Input

Output

IM4 – 0

Interrupt

Priority

00000

No Mask

XXXX1 Receiver

High

XXX1X Transmitter

XX1XX Line Turn-Around 3

X1XXX Bi-Directional

1XXXX Timer

Low

These bits represent the only visibility and control that the processor has into the operation of the remote interface controller The Remote Interface Configuration

RIC

accessible only by a remote processor provides further control functions See Remote Interface section for more information

173

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