FDC37M607 datasheet(129/182 Pages) SMSC

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Table 54 - Chip Level Registers

ADDRESS

DESCRIPTION

STATE

OSC

Default = 0x04, on

Vcc POR or

Reset_Drv hardware

signal.

0x24 R/W

Bit[0] Reserved

Bit [1] PLL Control

= 0 PLL is on (backward Compatible)

= 1 PLL is off

Bits[3:2] OSC

= 01

Osc is on, BRG clock is on.

= 10

Same as above (01) case.

= 00

Osc is on, BRG Clock Enabled.

= 11

Osc is off, BRG clock is disabled.

Bit [5:4] Reserved, set to zero

Bit [6] 16-Bit Address Qualification

= 0 12-Bit Address Qualification

= 1 16-Bit Address Qualification

Bit[7] Reserved

Chip Level

Vendor Defined

0x25

Reserved - Writes are ignored, reads return 0.

Configuration

Address Byte 0

Default

=0xF0 (Sysopt=0)

=0x70 (Sysopt=1)

on Vcc POR or

Reset_Drv

0x26

Bit[7:1] Configuration Address Bits [7:1]

Bit[0] = 0

See Note 1

Configuration

Address Byte 1

Default = 0x03

on Vcc POR or

Reset_Drv

0x27

Bit[7:0] Configuration Address Bits [15:8]

See Note 1

Default = 0x00

on VCC POR and

Hard Reset

0x28

Bits[7:0] Reserved - Writes are ignored, reads

return 0.

Chip Level

Vendor Defined

0x29 -0x2A

Reserved - Writes are ignored, reads return 0.

FDC37M607 Datasheet(PDF) 129 Page - SMSC Corporation

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