FDC37M607 datasheet(127/182 Pages) SMSC

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Chip Level (Global) Control/Configuration

Registers[0x00-0x2F]

The chip-level (global) registers lie in the

address range [0x00-0x2F]. The design MUST

use all 8 bits of the ADDRESS Port for register

selection. All unimplemented registers and bits

ignore writes and return zero when read.

The

INDEX

PORT

used

select

configuration register in the chip.

The DATA

PORT

is then used to access the selected

the Configuration Mode.

Table 53 - Chip Level Registers

ADDRESS

DESCRIPTION

STATE

Chip (Global) Control Registers

0x00 -

0x01

Reserved - Writes are ignored, reads return 0.

Config Control

Default = 0x00

on Vcc POR or

Reset_Drv

0x02 W

The hardware automatically clears this bit after the

write, there is no need for software to clear the bits.

Bit 0 = 1: Soft Reset. Refer to the "Configuration

Registers" table for the soft reset value for each

0x03 - 0x06

Reserved - Writes are ignored, reads return 0.

Logical Device #

Default = 0x00

on Vcc POR or

Reset_Drv

0x07 R/W

A write to this register selects the current logical

device.

This allows access to the control and

configuration registers for each logical device.

Note: the Activate command operates only on the

selected logical device.

Card Level

Reserved

0x08 - 0x1F

Reserved - Writes are ignored, reads return 0.

Chip Level, SMSC Defined

Device ID

Hard wired

= 0x47

0x20 R

read

only

which

provides

device

identification. Bits[7:0] = 0x47 when read.

Device Rev

Hard wired

= Current Revision

0x21 R

A read only register which provides device revision

information. Bits[7:0] = 0x00 when read.

FDC37M607 Datasheet(PDF) 127 Page - SMSC Corporation

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