FDC37M607 datasheet(124/182 Pages) SMSC

124 / 182 page

124

Notes: 1. HARD RESET: RESET_DRV pin asserted

2. SOFT RESET: Bit 0 of Configuration Control register set to one

3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram)

Table 52 - Configuration Registers

INDEX

TYPE

HARD RESET

Vcc

POR

SOFT

RESET

CONFIGURATION REGISTER

GLOBAL CONFIGURATION REGISTERS

0x02

0x00

Config Control

0x07

R/W

0x00

Logical Device Number

0x20

0x47

Device ID - hard wired

0x21

Current Revision

Device Rev - hard wired

0x22

R/W

0x00

Power Control

0x23

R/W

0x00

Power Mgmt

0x24

R/W

0x04

OSC

0x26

R/W

Sysopt=0: 0xF0

Sysopt=1: 0x70

Configuration Port Address Byte 0

0x27

R/W

Sysopt=0: 0x03

Sysopt=1: 0x03

Configuration Port Address Byte 1

0x2B

R/W

0x00

TEST 4

0x2C

R/W

0x00

TEST 5

0x2D

R/W

0x00

TEST 1

0x2E

R/W

0x00

TEST 2

0x2F

R/W

0x00

TEST 3

LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)

0x30

R/W

0x00

Activate

0x60,

0x61

R/W

0x03,

0xF0

0x03,0

xF0

Primary Base I/O Address

0x70

R/W

0x06

Primary Interrupt Select

0x74

R/W

0x02

DMA Channel Select

0xF0

R/W

0x0E

FDD Mode Register

0xF1

R/W

0x00

FDD Option Register

0xF2

R/W

0xFF

FDD Type Register

0xF4

R/W

0x00

FDD0

0xF5

R/W

0x00

FDD1

FDC37M607 Datasheet(PDF) 124 Page - SMSC Corporation

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