TDA9554PS datasheet(34/125 Pages) PHILIPS

34 / 125 page

2000 Jun 22

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Teletext decoder with

embedded

µ-Controller

TDA955X/6X/8X PS/N1 series

different priority level are received simultaneously, the

request with the highest priority level is serviced. If

requests of the same priority level are received

simultaneously, an internal polling sequence determines

which request is serviced. Thus, within each priority level

there is a second priority structure determined by the

polling sequence as defined in Table 4.

INTERRUPT VECTOR ADDRESS

The processor acknowledges an interrupt request by

executing a hardware generated LCALL to the appropriate

servicing routine. The interrupt vector addresseses are

shown in Table 4.

LEVEL/EDGE INTERRUPT

The external interrupt can be programmed to be either

level-activated or transition activated by setting or clearing

the IT0/1 bits in the Timer Control SFR(TCON).

The external interrupt INT1 differs from the standard

80C51 in that it is activated on both edges when in edge

sensitive mode. This is to allow software pulse width

measurement for handling remote control inputs.

Timer/Counter

Two 16 bit timers/counters are incorporated Timer0 and

Timer1. Both can be configured to operate as either timers

or event counters.

In Timer mode, the register is incremented on every

machine cycle. It is therefore counting machine cycles.

Since the machine cycle consists of 12 oscillator periods,

the count rate is 1/12 Fosc = 1MHz.

In Counter mode, the register is incremented in response

to a negative transition at its corresponding external pin

T0/1. Since the pins T0/1 are sampled once per machine

cycle it takes two machine cycles to recognise a transition,

this gives a maximum count rate of 1/24 Fosc = 0.5MHz.

There are six special function registers used to control the

timers/counters as defined in Table 6.

Source

Priority within level

Interrupt Vector

EX0

Highest

0003H

ET0

000BH

EX1

0013H

ET1

001BH

ECC

0023H

ES2

002BH

EBUSY

0033H

ET2PR

Lowest

003BH

Table 4

Interrupt Priority (within same level)

ITx

Level

Edge

Active low

INT0 = Negative Edge

INT1 = Positive and Negative Edge

Table 5

External Interrupt Activation

SFR

Address

TCON

88H

TMOD

89H

TL0

8AH

TH0

8BH

TL1

8CH

TH1

8DH

Table 6

Timer/Counter Registers

TF1 TR TF0 TR

IE1 IT1 IE0 IT0

Symbol

Position

Name and Signiﬁcance

TF1

TCON.7

Timer 1 overﬂow ﬂag. Set by hard-

ware on timer/counter overﬂow.

Cleared by hardware when processor

vectors to interrupt routine.

TR1

TCON.6

Timer 1 Run control bit. Set/cleared

by software to turn timer.counter

on/off.

TF0

TCON.5

Timer 0 overﬂow ﬂag. Set by hard-

ware on timer/counter overﬂow.

Cleared by hardware when processor

vectors to interrupt routine.

TR0

TCON.4

Timer 0 Run control bit. Set/cleared

by software to turn timer.counter

on/off.

Symbol

Position

Name and Signiﬁcance

IE1

TCON.3

Interrupt 1 Edge ﬂag. Set by hardware

when external interrupt edge

detected. Cleared when interrupt

processed.

IT1

TCON.2

Interrupt 1 Type control bit.

Set/cleared by software to specify fall-

ing edge/low level triggered external

interrupts.

IE0

TCON.1

Interrupt 0 Edge ﬂag. Set by hardware

when external interrupt edge

detected. Cleared when interrupt

processed.

IT0

TCON.0

Interrupt 0 Type control bit.

Set/cleared by software to specify fall-

ing edge/low level triggered external

interrupts.

Fig.11 Timer/Counter Control (TCON) register

TDA9554PS Datasheet(PDF) 34 Page - NXP Semiconductors

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