TDA9554PS datasheet(36/125 Pages) PHILIPS

36 / 125 page

2000 Jun 22

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Teletext decoder with

embedded

µ-Controller

TDA955X/6X/8X PS/N1 series

SFR and also writing a ‘1’ to the Port bit that the function

occupies.

PWM PULSE WIDTH MODULATORS

The device has four 6-bit Pulse Width Modulated (PWM)

outputs for analogue control of e.g. volume, balance, bass,

treble, brightness, contrast, hue and saturation. The PWM

outputs generate pulse patterns with a repetition rate of

21.33us, with the high time equal to the PWM SFR value

multiplied by 0.33us. The analogue value is determined by

the ratio of the high time to the repetition time, a D.C.

voltage proportional to the PWM setting is obtained by

means of an external integration network (low pass filter).

PWM Control

The relevant PWM is enabled by setting the PWM enable

bit PWxE in the PWMx Control register. The high time is

defined by the value PWxV<5:0>

TPWM TUNING PULSE WIDTH MODULATOR

The device has a single 14-bit PWM that can be used for

Voltage Synthesis Tuning. The method of operation is

similar to the normal PWM except the repetition period is

42.66us.

TPWM Control

Two SFRs are used to control the TPWM, they are TDACL

and TDACH. The TPWM is enabled by setting the TPWE

bit in the TDACH SFR. The most significant bits TD<13:7>

alter the high period between 0 and 42.33us. The 7 least

significant bits TD<6:0> extend certain pulses by a further

0.33us. e.g. if TD<6:0> = 01H then 1 in 128 periods will be

extended by 0.33us, if TD<6:0>=02H then 2 in 128 periods

will be extended.

The TPWM will not start to output a new value until TDACH

has been written to. Therefore, if the value is to be

changed, TACL should be written before TDACH.

SAD SOFTWARE A/D

Four successive approximation Analogue to Digital

Converters can be implemented in software by making use

of the on board 8-bit Digital to Analogue Converter and

Analogue Comparator.

SAD Control

The control of the required analogue input is done using

the channel select bits CH<1:0> in the SAD SFR, this

selects the required analogue input to be passed to one of

the inputs of the comparator. The second comparator input

is generated by the DAC whose value is set by the bits

SAD<7:0> in the SAD and SADB SFRs. A comparison

between the two inputs is made when the start compare bit

ST in the SAD SFR is set, this must be at least one

instruction cycle after the SAD<7:0> value has been set.

The result of the comparison is given on VHI one

instruction cycle after the setting of ST.

SAD Input Voltage

The external analogue voltage that is used for comparison

with the internally generated DAC voltage does not have

the same voltage range. The DAC has a lower reference

level of VSSA and an upper reference level of VSSA. The

resolution of the DAC voltage with a nominal value is

3.3/256 ~ 13mV. The external analogue voltage has a

lower value equivalent to VSSA and an upper value

equivalent to VDDP -Vtn, were Vtn is the threshold voltage

for an NMOS transistor. The reason for this is that the input

pins for the analogue signals (P3.0 to P3.3) are 5V tolerant

for normal port operations, i.e. when not used as analogue

input. To protect the analogue multiplexer and comparator

circuitry from the 5V, a series transistor is used to limit the

voltage. This limiting introduces a voltage drop equivalent

to Vtn (~0.6V) on the input voltage. Therefore, for an input

voltage in the range VDDP to VDDp-Vtn the SAD returns the

same comparison value.

SAD DC Comparator Mode

The SAD module incorporates a DC Comparator mode

which is selected using the ’DC_COMP’ control bit in the

SADB SFR. This mode enables the micro-controller to

detect a threshold crossing at the input to the selected

analogue input pin (P3.0, P3.1, P3.2 or P3.3) of the

Software A/D Converter. A level sensitive interrupt is

generated when the analogue input voltage level at the pin

falls below the analogue output level of the SAD D/A

converter.

This mode is intended to provide the device with a

wake-up mechanism from Power-Down or Idle when a

key-press on the front panel of the TV is detected.

VHI

MUX

4-1

8-bit

DAC

SAD<7:0>

ADC0

ADC1

ADC2

ADC3

CH<1:0>

VDDP

Fig.13 SAD Block Diagram

TDA9554PS Datasheet(PDF) 36 Page - NXP Semiconductors

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