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TDA9554PS Datasheet(PDF) 16 Page - NXP Semiconductors |
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TDA9554PS Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 125 page  2000 Jun 22 16 Philips Semiconductors Tentative Device Specification TV signal processor-Teletext decoder with embedded µ-Controller TDA955X/6X/8X PS/N1 series C1H R/W TXT1 EXT PKT OFF 8 BIT ACQ OFF X26 OFF FULL FIELD FIELD POLARITY H POLARITY V POLARITY C2H R/W TXT2 ACQ BANK REQ<3> REQ<2> REQ<1> REQ<0> SC<2> SC<1> SC<0> C3H W TXT3 - - - PRD<4> PRD<3> PRD<2> PRD<1> PRD<0> C4H R/W TXT4 OSD BANK ENABLE QUAD WIDTH ENABLE EAST/WES T DISABLE DOUBLE HEIGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE C5H R/W TXT5 BKGND OUT BKGND IN CORB OUT CORB IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN C6H R/W TXT6 BKGND OUT BKGND IN CORB OUT CORB IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN C7H R/W TXT7 STATUS ROW TOP CURSOR ON REVEAL BOTTOM/ TOP DOUBLE HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 C8H R/W TXT8 (Reserved) 0 FLICKER STOP ON HUNT DISABLE SPANISH PKT 26 RECEIVED WSS RECEIVED WSS ON CVBS1/ CVBS0 C9H R/W TXT9 CURSOR FREEZE CLEAR MEMORY A0 R<4> R<3> R<2> R<1> R<0> CAH R/W TXT10 0 0 C<5> C<4> C<3> C<2> C<1> C<0> CBH R/W TXT11 D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> CCH R TXT12 525/625 SYNC ROM VER<4> ROM VER<3> ROM VER<2> ROM VER<1> ROM VER<0> 1 VIDEO SIGNAL QUALITY CDH R/W TXT14 0 0 0 DISPLAY BANK PAGE<3> PAGE<2> PAGE<1> PAGE<0> CEH R/W TXT15 0 0 0 MICRO BANK BLOCK<3> BLOCK<2> BLOCK<1> BLOCK<0> D0H R/W PSW C AC F0 RS1 RS0 OV - P D2H R/W TDACL TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> D3H R/W TDACH TPWE 1 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8> D5H R/W PWM0 PW0E 1 PW0V<5> PW0V<4> PW0V<3> PW0V<2> PW0V<1> PW0V<0> D6H R/W PWM1 PW1E 1 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0> D7H R CCDAT1 CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3> CCD1<2> CCD1<1> CCD1<0> D8H R/W S1CON CR<2> ENSI STA STO SI AA CR<1> CR<0> D9H R S1STA STAT<4> STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0 DAH R/W S1DAT DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> DBH R/W S1ADR ADR<6> ADR<5> ADR<4> ADR<3> ADR<2> ADR<1> ADR<0> GC DCH R/W PWM3 PW3E 1 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0> E0H R/W ACC ACC<7> ACC<6> ACC<5> ACC<4> ACC<3> ACC<2> ACC<1> ACC<0> E4H R/W PWM2 PW2E 1 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0> ADD R/W Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Table 2 SFR Map |
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