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TDA9554PS Datasheet(PDF) 19 Page - NXP Semiconductors |
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TDA9554PS Datasheet(HTML) 19 Page - NXP Semiconductors |
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19 / 125 page  2000 Jun 22 19 Philips Semiconductors Tentative Device Specification TV signal processor-Teletext decoder with embedded µ-Controller TDA955X/6X/8X PS/N1 series P1CFGB<x>/P1CFGA<x> = 00 MODE 0 Open Drain. P1CFGB<x>/P1CFGA<x> = 01 MODE 1 Quasi Bi-Directional. P1CFGB<x>/P1CFGA<x> = 10 MODE2 High Impedance. P1CFGB<x>/P1CFGA<x> = 11 MODE3 Push Pull. P2CFGA Reserved P2CFGA<6> P2CFGA<5> P2CFGA<4> P2CFGA<3> P2CFGA<2> P2CFGA<1> P2CFGA<0> FFH P2CFGB Reserved P2CFGB<6> P2CFGB<5> P2CFGB<4> P2CFGB<3> P2CFGB<2> P2CFGB<1> P2CFGB<0> 00H P2CFGB<x>/P2CFGA<x> = 00 MODE 0 Open Drain. P2CFGB<x>/P2CFGA<x> = 01 MODE 1 Quasi Bi-Directional. P2CFGB<x>/P2CFGA<x> = 10 MODE2 High Impedance. P2CFGB<x>/P2CFGA<x> = 11 MODE3 Push Pull. P3CFGA Reserved Reserved Reserved Reserved P3CFGA<3> P3CFGA<2> P3CFGA<1> P3CFGA<0> FFH P3CFGB Reserved Reserved Reserved Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0> 00H P3CFGB<x>/P3CFGA<x> = 00 MODE 0 Open Drain. P3CFGB<x>/P3CFGA<x> = 01 MODE 1 Quasi Bi-directional. P3CFGB<x>/P3CFGA<x> = 10 MODE2 High Impedance. P3CFGB<x>/P3CFGA<x> = 11 MODE3 Push Pull. PCON SMOD ARD RFI WLE GF1 GF0 PD IDL 00H SMOD UART Baud Rate Double Control. ARD Auxiliary RAM Disable, All MOVX instructions access the external data memory. RFI Disable ALE during internal access to reduce Radio Frequency Interference. WLE Watch Dog Timer enable. GF1 General purpose flag. GF0 General purpose flag. PD Power-down activation bit. IDL Idle mode activation bit. PSW C AC F0 RS<1> RS<0> OV - P 00H C Carry Bit. AC Auxiliary Carry bit. F0 Flag 0, General purpose flag. RS<1:0> Register Bank selector bits. RS<1:0> = 00, Bank0 (00H - 07H). RS<1:0> = 01, Bank1 (08H - 0FH). RS<1:0> = 10, Bank2 (10H - 17H). RS<1:0> = 11, Bank3 (18H - 1FH). OV Overflow flag. Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RESET Table 3 SFR Bit description |
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