TDA9554PS datasheet(56/125 Pages) PHILIPS

56 / 125 page

2000 Jun 22

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Teletext decoder with

embedded

µ-Controller

TDA955X/6X/8X PS/N1 series

DEFINING CHARACTERS

The DRC RAM is mapped on to the 80C51 RAM address

space and starts at location 8800H. The character matrix

is 12 bits wide and therefore requires two bytes to be

written for each word, the first byte (even addresses),

addresses the lower 8 bits and the second byte (odd

addresses) addresses the upper 4 bits.

For characters of 9, 10 or 16 lines high the pixel

information starts in the first address and continues

sequentially for the required number of addresses.

Characters of 13 lines high are defined with an initial offset

of 1 address, this is to allow for correct generation of

fringing across boundaries of clustered characters (see

Fig.27). The characters continue sequentially for 13 lines

after which a further line can again be used for generation

of correct fringing across boundaries of clustered

characters.

DRCs are defined by writing data to the DRC RAM using

the 80C51 MOVX command. Setting bits 3 to 9 of the first

line of a 12 wide by 16 line character would require setting

the high byte of the 80C51 data pointer to 88H, the low

byte of the 80C51 data pointer to 00H, using the MOVX

command to load address 8800H with data F8H,

incrementing the data pointer, and finally using the MOVX

command to load address 8801H with data 03H.

Display Synchronization

The horizontal and vertical synchronizing signals from the

TV deflection are used as inputs. Both signals can be

inverted before being delivered to the Phase Selector

section.

CC: The polarity is controlled using either VPOL or HPOL

in REG2:Text position Vertical.

TXT: SFRs bits TXT1.HPOL & TXT1.VPOL control the

polarity.

A line locked 12 MHz clock is derived from the 12MHz free

running oscillator by the Phase Selector. This line locked

clock is used to clock the whole of the Display block.

The H & V Sync signals are synchronized with the 12 MHz

clock before being used in the display section.

Video/Data Switch (Fast Blanking) Polarity

The polarity of the Video/Data (Fast Blanking) signal can

be inverted. The polarity is set with the VDSPOL in REG7:

RGB Brightness register.

Video/Data Switch Adjustment

To take into account the delay between the RGB values

and the VDS signal due to external buffering, the VDS

signal can be moved in relation to the RGB signals. The

VDS signal can be set to be either a clock cycle before or

after the RGB signal, or coincident with the RGB signal.

This is done using VDEL<2:0> in REG15:Configuration.

CHAR 1

CHAR 2

CHAR 30

CHAR 31

CHAR 0

Address

12 bits

Micro Address

8800

881F

8820

883F

8840

885F

8BFF

8BE0

8BDF

8BC0

Char Code

80h

81h

82h

9Eh

9Fh

Fig.26 Organisation of DRC RAM

Top Left

Bottom Right

Fringing

Top Line

Hex

003

00C

030

0C0

300

C00

300

C00

030

00C

003

000

440

Line 13 from

character above

Line 1 from

character below

Fringing

1A8

000

Pixel

Line not used

Line

No.

Bottom Line

MSB

LSB

Fig.27 13 Line High DRC’s Character Format

VDSP

VDS

Condition

RGB display

Video Display

RGB display

Video Display

Table 25 Fast Blanking Signal Polarity

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