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TDA9554PS Datasheet(PDF) 68 Page - NXP Semiconductors

Part # TDA9554PS
Description  TV signal processor-Teletext decoder with embedded m-Controller
PDF  125 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA9554PS Datasheet(HTML) 68 Page - NXP Semiconductors

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2000 Jun 22
68
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded
µ-Controller
TDA955X/6X/8X PS/N1 series
Table 34 Outputs TV-processor
FUNCTION
SUBADDR
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
Output status bytes
00
POR
IFI
LOCK
SL
CD3
CD2
CD1
CD0
01
XPR
NDF
FSI
IVW
WBC
HBC
BCF
IN2
02
SUP
AGC
0
QSS
AFA
AFB
FMW
FML
03
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
04
SN1
SN0
XXXXXX
Explanation input control data TV-processor
Table 35 Timing of ‘wide blanking’
Table 36 Soft clipping level
Table 37 Peak White Limiting; note 1
Note
1. CVBS/Y input signal at which the Peak White Limiting
is activated. Nominal input signal: 1.0 VBL-WH.
Table 38 Off-set IF demodulator
Table 39 Horizontal parallelogram
Table 40
Horizontal bow
Table 41
Hue control
Table 42
Horizontal shift
DAC SETTING
SETTING
0
3.5 / 7.8
µs
0F
5.9 / 10.2
µs
SOC1
SOC0
VOLTAGE DIFFERENCE BETWEEN
SOFT CLIPPING AND PWL
0
0
0% above PWL level
0
1
5% above PWL level
1
0
10% above PWL level
1
1
soft clipping off
DAC SETTING
CONTROL
00
0.55 VBL-WH
0F
0.85 VBL-WH
DAC SETTING
CONTROL
0
tbf
20
no correction
3F
tbf
DAC SETTING
CONTROL
0
screen top 0.5
µs delayed and screen
bottom 0.5
µs advanced with respect
to centre
20
no correction
3F
screen top 0.5
µs advanced and
screen bottom 0.5
µs delayed with
respect to centre
DAC SETTING
CONTROL
0
screen top and bottom 0.5
µs delayed
with respect to centre
20
no correction
3F
screen top and bottom 0.5
µs
advanced with respect to centre
DAC SETTING
CONTROL
0
−45°
20
0
°
3F
+45
°
DAC SETTING
CONTROL
0
−2 µs
20
0
3F
+2
µs



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