| Electronic Components Datasheet Search |
|
AD9554 Datasheet(PDF) 112 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9554 Datasheet(HTML) 112 Page - Analog Devices |
|
112 / 116 page ![]() AD9554 Data Sheet Rev. D | Page 112 of 116 Address Bits Bit Name Description 0x1688 [7:3] Reserved Default: 00000b. [2:1] APLL_2 manual cal level APLL_2 reference voltage used during APLL_0 calibration. Set these bits (and issue an IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure optimal performance over temperature and voltage extremes. These bits must be set only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9. 00b = Reference Voltage 0 (default). 01b = Reference Voltage 1 (recommended). 10b = Reference Voltage 2. 11b = Reference Voltage 3. 0 En APLL_2 man cal level Enables manual control of the VCAL reference setting for APLL_2. 0 = manual control disabled (default). 1 = manual control enabled (recommended). 0x1788 [7:3] Reserved Default: 00000b. [2:1] APLL_3 manual cal level APLL_3 reference voltage used during APLL_0 calibration. Set these bits (and issue an IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure optimal performance over temperature and voltage extremes. These bits must be set only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9. 00b = Reference Voltage 0 (default). 01b = Reference Voltage 1 (recommended). 10b = Reference Voltage 2. 11b = Reference Voltage 3. 0 En APLL_3 man cal level Enables manual control of the VCAL reference setting for APLL_3. 0 = manual control disabled (default). 1 = manual control enabled (recommended). Table 154. Multifunction Pin Output Functions (D7 = 1) Bits[D7:D0] Value Output Function Source Proxy 0x80 Static Logic 0 None 0x81 Static Logic 1 None 0x82 System clock divided by 32 None 0x83 Watchdog timer output; this is a strobe whose duration equals (32/(one system clock period)) when timer expires None 0x84 SYSCLK PLL calibration busy Register 0x0D01, Bit 2 0x85 SYSCLK PLL lock detected Register 0x0D01, Bit 0 0x86 SYSCLK PLL stable Register 0x0D01, Bit 1 0x87 All PLLs locked (logical AND of 0x88, 0x89, 0x8A, 0x8B) Register 0x0D01, Bits[7:4] 0x88 (DPLL_0 phase lock) AND (APLL_0 lock) AND (SYSCLK PLL lock) Register 0x0D01, Bit 4 0x89 (DPLL_1 phase lock) AND (APLL_1 lock) AND (SYSCLK PLL lock) Register 0x0D01, Bit 5 0x8A (DPLL_2 phase lock) AND (APLL_2 lock) AND (SYSCLK PLL lock) Register 0x0D01, Bit 6 0x8B (DPLL_3 phase lock) AND (APLL_3 lock) AND (SYSCLK PLL lock) Register 0x0D01, Bit 7 0x8C EEPROM upload (write to EEPROM) in progress Register 0x0D00, Bit 0 0x8D EEPROM download (read from EEPROM) in progress Register 0x0D00, Bit 1 0x8E EEPROM fault detected Register 0x0D00, Bit 2 0x90 All IRQs: (IRQ_common) OR (IRQ_PLL_0) OR (IRQ_PLL_1) OR (IRQ_PLL_2) OR (IRQ_PLL_3) None 0x91 IRQ_common None 0x92/0x93/0x94/0x95 IRQ_PLL_0/IRQ_PLL_1/IRQ_PLL_2/IRQ_PLL_3 None 0xA0/0xA1/0xA2/0xA3 REFA/REFB/REFC/REFD fault Register 0x0D02/Register 0x0D03/ Register 0x0D04/Register 0x0D05, Bit 2 0xA8/0xA9/0xAA/0xAB REFA/REFB/REFC/REFD valid Register 0x0D02/Register 0x0D03/ Register 0x0D04/Register 0x0D05, Bit 3 0xB0 REFA active (any PLL) Register 0x0D02, Bit 4||Bit 5||Bit 6||Bit 7 0xB1 REFB active (any PLL) Register 0x0D03, Bit 4||Bit 5||Bit 6||Bit 7 0xB2 REFC active (any PLL) Register 0x0D04, Bit 4||Bit 5||Bit 6||Bit 7 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |