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AD9554 Datasheet(PDF) 114 Page - Analog Devices |
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AD9554 Datasheet(HTML) 114 Page - Analog Devices |
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114 / 116 page  AD9554 Data Sheet Rev. D | Page 114 of 116 Bits[D7:D0] Value Output Function Source Proxy 0xF4 DPLL_3 active Logical OR of Bit 7 in Register 0x0D02 through Register 0x0D05 0xF5 DPLL_3 in free run mode Register 0x0D81, Bit 0 0xF6 DPLL_3 in holdover Register 0x0D81, Bit 1 0xF7 DPLL_3 in switchover Register 0x0D81, Bit 2 0xF8 DPLL_3 history available Register 0x0D82, Bit 0 0xF9 DPLL_3 history updated Register 0x0D0F, Bit 4 (IRQ does not need to be set for this setting to work) 0xFA DPLL_3 clamp Register 0x0D82, Bit 1 0xFB DPLL_3 phase slew limited Register 0x0D82, Bit 2 0xFC PLL_3 clock distribution sync pulse None 0xFD DPLL_3 demapping controller clamped Register 0x0D82, Bit 3 0xFE to 0xFF Reserved None Table 155. Multifunction Pin Input Functions (D7 = 0) Bits[D7:D0] Value Input Function Destination Proxy 0x00 No function None 0x01 IO_UPDATE Register 0x000F, Bit 0 0x02 Full power-down Register 0x0A00, Bit 0 0x03 Clear watchdog timer Register 0x0A05, Bit 7 0x04 Soft sync all Register 0x0A00, Bit 3 0x10 Clear all IRQs Register 0x0A05, Bit 0 0x11 Clear common IRQs Register 0x0A05, Bit 1 0x12 Clear DPLL_0 IRQs Register 0x0A05, Bit 2 0x13 Clear DPLL_1 IRQs Register 0x0A05, Bit 3 0x14 Clear DPLL_2 IRQs Register 0x0A05, Bit 4 0x15 Clear DPLL_3 IRQs Register 0x0A05, Bit 5 0x20/0x21/0x22/0x23 Force fault REFA/REFB/REFC/REFD Register 0x0A03, Bits[3:0] 0x28/0x29/0x2A/0x2B Force validation timeout REFA/REFB/REFC/REFD Register 0x0A02, Bits[3:0] 0x40 PLL_0 power-down Register 0x0A20, Bit 0 0x41 DPLL_0 user free run Register 0x0A22, Bit 0 0x42 DPLL_0 user holdover Register 0x0A22, Bit 1 0x43 DPLL_0 tuning word history reset Register 0x0A23, Bit 1 0x44 DPLL_0 increment phase offset Register 0x0A24, Bit 0 0x45 DPLL_0 decrement phase offset Register 0x0A24, Bit 1 0x46 DPLL_0 reset phase offset Register 0x0A24, Bit 2 0x48 APLL_0 soft sync Register 0x0A20, Bit 2 0x49 PLL_0 disable all output drivers Register 0x0A21, Bits[3:2] 0x4A PLL_0 disable OUT0A Register 0x0A21, Bit 2 0x4B PLL_0 disable OUT0B Register 0x0A21, Bit 3 0x4C PLL_0 manual reference input selection, Bit 0 Register 0x0A22, Bit 5 0x4D PLL_0 manual reference input selection, Bit 1 Register 0x0A22, Bit 6 0x50 PLL_1 power-down Register 0x0A40, Bit 0 0x51 DPLL_1 user free run Register 0x0A42, Bit 0 0x52 DPLL_1 user holdover Register 0x0A42, Bit 1 0x53 DPLL_1 tuning word history reset Register 0x0A43, Bit 1 0x54 DPLL_1 increment phase offset Register 0x0A44, Bit 0 0x55 DPLL_1 decrement phase offset Register 0x0A44, Bit 1 0x56 DPLL_1 reset phase offset Register 0x0A44, Bit 2 0x58 APLL_1 soft sync Register 0x0A40, Bit 2 0x59 PLL_1 disable all output drivers Register 0x0A41, Bits[3:2] 0x5A PLL_1 disable OUT1A Register 0x0A41, Bit 2 0x5B PLL_1 disable OUT1B Register 0x0A41, Bit 3 |
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