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AD9554 Datasheet(PDF) 115 Page - Analog Devices

Part # AD9554
Description  Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  116 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9554 Datasheet(HTML) 115 Page - Analog Devices

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Data Sheet
AD9554
Rev. D | Page 115 of 116
Bits[D7:D0] Value
Input Function
Destination Proxy
0x5C
PLL_1 manual reference input selection, Bit 0
Register 0x0A42, Bit 5
0x5D
PLL_1 manual reference input selection, Bit 1
Register 0x0A42, Bit 6
0x60
PLL_2 power-down
Register 0x0A60, Bit 0
0x61
DPLL_2 user free run
Register 0x0A62, Bit 0
0x62
DPLL_2 user holdover
Register 0x0A62, Bit 1
0x63
DPLL_2 tuning word history reset
Register 0x0A63, Bit 1
0x64
DPLL_2 increment phase offset
Register 0x0A64, Bit 0
0x65
DPLL_2 decrement phase offset
Register 0x0A64, Bit 1
0x66
DPLL_2 reset phase offset
Register 0x0A64, Bit 2
0x68
APLL_2 soft sync
Register 0x0A60, Bit 2
0x69
PLL_2 disable all output drivers
Register 0x0A61, Bits[3:2])
0x6A
PLL_2 disable OUT2A
Register 0x0A61, Bit 2
0x6B
PLL_2 disable OUT2B
Register 0x0A61, Bit 3
0x6C
PLL_2 manual reference input selection, Bit 0
Register 0x0A62, Bit 5
0x6D
PLL_2 manual reference input selection, Bit 1
Register 0x0A62, Bit 6
0x70
PLL_2 power-down
Register 0x0A60, Bit 0
0x71
DPLL_3 user free run
Register 0x0A82, Bit 0
0x72
DPLL_3 user holdover
Register 0x0A82, Bit 1
0x73
DPLL_3 tuning word history reset
Register 0x0A83, Bit 1
0x74
DPLL_3 increment phase offset
Register 0x0A84, Bit 0
0x75
DPLL_3 decrement phase offset
Register 0x0A84, Bit 1
0x76
DPLL_3 reset phase offset
Register 0x0A84, Bit 2
0x78
APLL_3 soft sync
Register 0x0A80, Bit 2
0x79
PLL_3 disable all output drivers
Register 0x0A81, Bits[3:2]
0x7A
PLL_3 disable OUT3A
Register 0x0A81, Bit 2
0x7B
PLL_3 disable OUT3B
Register 0x0A81, Bit 3
0x7C
PLL_3 manual reference input selection, Bit 0
Register 0x0A82, Bit 5
0x7D
PLL_3 manual reference input selection, Bit 1
Register 0x0A82, Bit 6
0x7E to 0x7F
Reserved
None



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