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AD9554 Datasheet(PDF) 113 Page - Analog Devices |
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AD9554 Datasheet(HTML) 113 Page - Analog Devices |
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113 / 116 page  Data Sheet AD9554 Rev. D | Page 113 of 116 Bits[D7:D0] Value Output Function Source Proxy 0xB3 REFD active (any PLL) Register 0x0D05, Bit 4||Bit 5||Bit 6||Bit 7 0xC0 DPLL_0 phase locked Register 0x0D20, Bit 1 0xC1 DPLL_0 frequency locked Register 0x0D20, Bit 2 0xC2 APLL_0 frequency lock Register 0x0D20, Bit 3 0xC3 APLL_0 cal in process Register 0x0D20, Bit 4 0xC4 DPLL_0 active Logical OR of Bit 4 in Register 0x0D02 through Register 0x0D05 0xC5 DPLL_0 in free run mode Register 0x0D21, Bit 0 0xC6 DPLL_0 in holdover Register 0x0D21, Bit 1 0xC7 DPLL_0 switching Register 0x0D21, Bit 2 0xC8 DPLL_0 history available Register 0x0D22, Bit 0 0xC9 DPLL_0 history updated Register 0x0D0C, Bit 4 (IRQ does not need to be set for this setting to work) 0xCA DPLL_0 clamp Register 0x0D22, Bit 1 0xCB DPLL_0 phase slew limited Register 0x0D22, Bit 2 0xCC PLL_0 clock distribution sync pulse None 0xCD DPLL_1 demapping controller clamped Register 0x0D22, Bit 3 0xD0 DPLL_1 phase locked Register 0x0D40, Bit 1 0xD1 DPLL_1 frequency locked Register 0x0D40, Bit 2 0xD2 APLL_1 frequency lock Register 0x0D40, Bit 3 0xD3 APLL_1 cal in process Register 0x0D40, Bit 4 0xD4 DPLL_1 active Logical OR of Bit 5 in Register 0x0D02 through Register 0x0D05 0xD5 DPLL_1 in free run mode Register 0x0D41, Bit 0 0xD6 DPLL_1 in holdover Register 0x0D41, Bit 1 0xD7 DPLL_1 in switchover Register 0x0D41, Bit 2 0xD8 DPLL_1 history available Register 0x0D42, Bit 0 0xD9 DPLL_1 history updated Register 0x0D0F, Bit 4 (IRQ does not need to be set for this setting to work) 0xDA DPLL_1 clamp Register 0x0D42, Bit 1 0xDB DPLL_1 phase slew limited Register 0x0D42, Bit 2 0xDC PLL_1 clock distribution sync pulse None 0xDD DPLL_1 demapping controller clamped Register 0x0D42, Bit 3 0xE0 DPLL_2 phase locked Register 0x0D60, Bit 1 0xE1 DPLL_2 frequency locked Register 0x0D60, Bit 2 0xE2 APLL_2 frequency lock Register 0x0D60, Bit 3 0xE3 APLL_2 cal in process Register 0x0D60, Bit 4 0xE4 DPLL_2 active Logical OR of Bit 6 in Register 0x0D02 through Register 0x0D05 0xE5 DPLL_2 in free run mode Register 0x0D61, Bit 0 0xE6 DPLL_2 in holdover Register 0x0D61, Bit 1 0xE7 DPLL_2 in switchover Register 0x0D61, Bit 2 0xE8 DPLL_2 history available Register 0x0D62, Bit 0 0xE9 DPLL_2 history updated Register 0x0D0C, Bit 4 (IRQ does not need to be set for this setting to work) 0xEA DPLL_2 clamp Register 0x0D62, Bit 1 0xEB DPLL_2 phase slew limited Register 0x0D62, Bit 2 0xEC PLL_2 clock distribution sync pulse None 0xED DPLL_2 demapping controller clamped Register 0x0D62, Bit 4 0xF0 DPLL_3 phase locked Register 0x0D80, Bit 1 0xF1 DPLL_3 frequency locked Register 0x0D80, Bit 2 0xF2 APLL_3 frequency lock Register 0x0D80, Bit 3 0xF3 APLL_3 cal in process Register 0x0D80, Bit 4 |
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