S5335 datasheet(107/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

107

Data Sheet

ADD-ON BUS INTERFACE

This chapter describes the Add-On bus interface for

the S5335. The S5335 is designed to support connec-

tion to a variety of microprocessor buses and/or

peripheral devices. The Add-On interface controls

S5335 operation through the Add-On Operation Reg-

isters. These registers act as the Pass-Thru, FIFO,

non-volatile memory and mailbox interfaces as well as

offering control and status information.

Depending on the register being accessed, the inter-

face may be synchronous or asynchronous. To

enhance performance and simplify Add-On logic

design, some registers allow direct access with a sin-

gle device input pin. Asynchronous burst read and

write FIFO operations are not recommended. The fol-

lowing sections describe the various interfaces to the

PCI bus and how they are accessed from the Add-On

interface.

ADD-ON OPERATION REGISTER

ACCESSES

The S5335 Add-On bus interface is very similar to that

of a memory or peripheral device found in a micropro-

cessor-based system. A 32-bit data bus with individual

read and write strobes, a chip enable and byte

enables are provided. Other Add-On interface signals

are provided to simplify Add-On logic design.

Accesses to the S5335 registers are done primarily

synchronously to BPCLK. For S5335 functions that

are compatible with an Add-On microprocessor inter-

face, it is helpful to allow an asynchronous interface,

as the processor may not operate at the PCI bus clock

frequency.

Add-On Interface Signals

The Add-On interface provides a small number of sys-

tem signals to allow the Add-On to monitor PCI bus

activity, indicate status conditions (interrupts), and

allow Add-On bus configuration. A standard bus inter-

face is provided for Add-On Operation Register

accesses.

System Signals

BPCLK and SYSRST# allow the Add-On interface to

monitor the PCI bus status. BPCLK is a buffered ver-

sion of the PCI clock. The PCI clock can operate from

0 MHz to 33 MHz. SYSRST# is a buffered version of

the PCI reset signal, and may also be toggled by host

application software through bit 24 of the Bus Master

Control/Status Register (MCSR).

IRQ# is the Add-On interrupt output. This signal is

active low and can indicate a number of conditions.

Add-On interrupts may be generated from the mailbox

or FIFO interfaces. The exact conditions which gener-

ate an interrupt are discussed in the mailbox and FIFO

chapters. The interrupt output is deasserted when

acknowledged by an access to the Add-On Interrupt

Control/Status Register (AINT). All interrupt sources

are cleared by writing a one to the corresponding inter-

rupt bit.

The MODE input on the Add-On interface configures

the datapath width for the Add-On interface. MODE

low indicates a 32-bit data bus. MODE high indicates a

16-bit data bus. For 16-bit operation, BE3# is rede-

fined as ADR1, providing an extra address input.

ADR1 selects the low or high words of the 32-bit

S5335 Add-On Operation Registers.

Simple register accesses to the S5335 Add-On Opera-

tion Registers take two forms: synchronous to BPCLK

and asynchronous. The following signals are required

to complete a register access to the S5335.

BE[3:0]#

Byte Enable Inputs. These S5335 inputs

identify valid byte lanes during Add-On transac-

tions. When MODE is set for 16-bit operation,

BE2# is not defined and BE3# becomes ADR1.

ADR[6:2]

Address Inputs. These address pins identify

the specific Add-On Operation Register being

accessed. When configured for 16-bit operation

(MODE=1), an additional input, ADR1 is available

to allow the 32-bit operation registers to be

accessed with two 16-bit cycles.

RD#

Read Strobe Input.

WR#

Write Strobe Input.

SELECT#

Chip Select Input. This input identifies a

valid S5335 access.

DQ[31:0]

Bidirectional Data Bus. These I/O pins are

the S5335 data bus. When configured for 16-bit

operation, only DQ[15:0] are valid.

In addition, there are dedicated signals for FIFO

accesses (RDFIFO# and WRFIFO#) and Pass-Thru

address accesses (PTADR#). These are discussed

separately in the FIFO and Pass-Thru sections of this

chapter.

The internal interfaces of the S5335 allow Add-On

Operation Registers to be accessed asynchronous to

BPCLK (synchronous to the rising edge of the read or

write strobe). The exception to this is the Add-On Gen-

eral Control/Status Register. This is due to the async

nature of FIFO status bits changing as the PCI bus

reads data. For Pass-Thru operations, the Pass-Thru

Data Register accesses are synchronous to BPCLK to

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