S5335 datasheet(104/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

104

Data Sheet

Bus Acquisition

Once GNT# is asserted, giving bus ownership to the

S5335, the S5335 must wait until the PCI bus

becomes idle. This delay is called bus acquisition

latency and involves the state of the signals FRAME#

and IRDY#. The current bus master must complete its

current transaction before the S5335 may drive the

bus. Table 56 depicts the four possible combinations

of FRAME# and IRDY# with their interpretation.

Target Latency

The PCI specification requires that a selected target

relinquish the bus should an access to that target

require more than eight PCI clock periods (16 clocks

for the first data phase in a burst). Slow targets can

exist within the PCI specification by using the target

initiated retry. This prevents slow target devices from

potentially monopolizing the PCI bus and also allows

more accurate estimations for bus access latency.

Target Locking

It is possible for a PCI bus master to obtain exclusive

access to a target (“locking”) through use of the PCI

bus signal LOCK#. LOCK# is different from the other

PCI bus signals because its ownership may belong to

any bus master, even if it does not currently have own-

ership of the PCI bus. The ownership of LOCK#, if not

already claimed by another master, may be achieved

by the current PCI bus master on the clock period fol-

lowing the initial assertion of FRAME#. Figure 61

describes the signal relationship for establishing a

lock. The ownership of LOCK#, once established, per-

sists even while other bus masters control the bus.

Ownership can only be relinquished by the master

which originally established the lock.

Figure 61. Engaging the LOCK# Signal

Table 56. Possible Combinations of FRAME# and IRDY#

FRAME#

IRDY#

Description

deasserted

Bus Idle

deasserted

asserted

The initiator is ready to complete the last data transfer of a transaction.

asserted

deasserted

An Initiator has a transaction in progress but is not able to complete the data transfer on this

clock.

asserted

An initiator has a transaction in progress and is able to complete a data transfer.

PCI CLOCK

FRAME #

LOCK #

AD[31:0]

IRDY#

TRDY#

DEVSEL#

ADDRESS

DATA

TARGET

BECOMES

LOCKED

LOCK

MECHANISM

AVAILABLE

UPON FIRST

ACCESS

LOCK MECHANISM

AVAILABLE

LOCK ESTABLISHED

LOCK MAINTAINED

BUS

IDLE

STILL DRIVEN BY PREVIOUS

OWNER (TARGET IS LOCKED)

(T)

(I)

(I) = DRIVEN BY INITIATOR

(T) = DRIVEN BY TARGET

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