S5335 datasheet(134/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

134

Data Sheet

Additional Status/Control Signals for Add-On Initi-

ated Bus Mastering

If a serial non-volatile memory is used to configure the

S5335, and the device is configured for Add-On initi-

ated bus mastering, two additional FIFO status signals

and four additional control signals are available to the

Add-On interface. The FRF and FWE outputs provide

additional FIFO status information. Inputs FRC#,

FWC#, AMREN, and AMWEN provide additional FIFO

control. Applications may use these signals to monitor/

control FIFO flags and PCI bus requests. These new

signals are some of the lines that were used for byte-

wide nvram interface, but now are reconfigured. The

reconfigured lines are as follows:

Outputs:

E_ADDR (15) FRF

FIFO Read Full: Indicates that the PCI to Add-On

FIFO is full.

E_ADDR (14) FWE

FIFO Write Empty: Indicates the last Add-On to PCI

FIFO. Data has transferred to a final buffer and is

queued for transfer, FIFO is empty.

Inputs:

EQ (7) AMWEN

Add-On bus Mastering Write ENable: This input is

driven high to enable bus master writes.

EQ (6) AMREN

Add-On bus Mastering Read ENable: This input is

driven high to enable bus master reads.

EQ (5) FRC#

FIFO Read Clear: This line is driven low to clear the

PCI to Add-On FIFO.

EQ (4) FWC#

FIFO Write Clear: This line is driven low to clear the

Add-On to PCI FIFO.

FRF (PCI to Add-On FIFO full) and FWE (Add-On to

PCI FIFO empty) supplement the RDEMPTY and

WRFULL status indicators. These additional status

outputs provide additional FIFO status information for

Add-On FIFO control logic.

Figure 82. Synchronous FIFO Register Burst RDFIFO# Access Example

BPCLK

DQ[31:0]

RDFIFO#

RDEMPTY

Data 1

Data 2

Data 0

FIFO Pointer Advances

Status Before Read

New Status

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