SH7616 datasheet(133/935 Pages) RENESAS

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Section 3 Oscillator Circuits and Operating Modes

Rev. 2.00 Mar 09, 2006 page 107 of 906

REJ09B0292-0200

Section 3 Oscillator Circuits and Operating Modes

3.1

Overview

Operation of the on-chip clock pulse generator, and CS0 area bus width specification, are

controlled by the operating mode pins. A crystal resonator or external clock can be selected as the

clock source.

3.2

On-Chip Clock Pulse Generator and Operating Modes

3.2.1

Clock Pulse Generator

A block diagram of the on-chip clock pulse generator circuit is shown in figure 3.1.

CAP1

CKIO

MD2

MD0

MD1

CKPACK*

Oscillator

On/Off

PLL circuit 1

PLL circuit 2

×1, ×2, ×4

CAP2

EXTAL

XTAL

CKPREQ/CKM

Clock mode control circuit

DIVP

1/1

1/2

1/4

Note: See section 21.4.4, Clock Pause Function.

External interface

clock

CPU/DSP core

clock

Peripheral module

clock

The relationship between the

internal clock frequencies is:

φ ≥ Eφ ≥ Pφ.

Maximum frequencies are:

φ, Eφ ≤ 62.5 MHz, Pφ ≤ 31.25 MHz.

DIVE

1/1

1/2

1/4

DIVM

1/1

1/2

1/4

φ system clock

Figure 3.1 Block Diagram of Clock Pulse Generator Circuit

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