SH7616 datasheet(135/935 Pages) RENESAS

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Section 3 Oscillator Circuits and Operating Modes

Rev. 2.00 Mar 09, 2006 page 109 of 906

REJ09B0292-0200

3.2.2

Clock Operating Mode Settings

Table 3.2 lists the functions and operation of clock modes 0 to 6.

Table 3.2

Operating Modes

Clock Mode

Function/Operation

Clock Source

PLL circuits 1 and 2 operate. A clock is output with the same

phase (with the same frequency as E

φ) as the internal clocks

φ, Eφ, Pφ) from the CKIO pin

PLL circuits 1 and 2 can be switched between the operating

and halted states by means of control bits in the frequency

modification register (FMR). The CKIO pin can also be placed

in the high-impedance state

Normally, mode 0 should be used.

Crystal resonator/

external clock input

PLL circuits 1 and 2 operate. A clock (with the same

frequency as E

φ) 1/4 φ cycle in advance of the chip's internal

system clock

φ is output from the CKIO pin.

PLL circuits 1 and 2 can be switched between the operating

and halted states by means of control bits in the frequency

modification register (FMR). The CKIO pin can also be placed

in the high-impedance state. However, clock phase shifting is

not performed when PLL circuit 1 is halted.

Normally, mode 0 should be used.

Only PLL circuit 2 operates. The clock from PLL circuit 2 is

output from the CKIO pin (having the same frequency as the

φ). As PLL circuit 1 does not operate, phases are not

matched in this mode

PLL circuit 2 can be switched between the operating and

halted states by means of a control bit in the frequency

modification register (FMR). The CKIO pin can also be placed

in the high-impedance state

Only PLL circuit 2 operates. The CKIO pin is high-impedance

PLL circuit 2 can be switched between the operating and

halted states by means of a control bit in the frequency

modification register (FMR)

Only PLL circuit 1 operates. Operate PLL circuit 1 when

operating with synchronization of the phases of the clock

input from the CKIO pin and the internal clocks (I

φ, Eφ, Pφ).

PLL circuit 2 does not operate in this mode

PLL circuit 1 can be switched between the operating and

halted states by means of a control bit in the frequency

modification register (FMR)

External clock input

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