SH7616 datasheet(140/935 Pages) RENESAS

140 / 935 page

Section 3 Oscillator Circuits and Operating Modes

Rev. 2.00 Mar 09, 2006 page 114 of 906

REJ09B0292-0200

3.2.5

Operating Frequency Selection by Register

Using the frequency modification register (FMR), it is possible to specify the operating frequency

division ratio for the internal clocks (I

φ, Eφ, Pφ). The internal clock frequency is determined under

the control of PLL circuits 1 and 2 and dividers DIVM, DIVE, and DIVP.

Frequency Modification Register (FMR): The frequency modification register is initialized only

by a power-on reset via the

RES pin, and not by an internal reset resulting from WDT overflow.

Its initial value depends on the settings of pins MD2–MD0. Table 3.4 shows the relationship

between the MD2–MD0 pin combinations and the initial value of the frequency modification

Table 3.4

Relationship between Clock Mode Pin Settings and Initial Value of Frequency

Modification Register

Clock Mode

MD2

MD1

MD0

Initial Value

Mode 0

000H'00

Mode 1

Mode 2

010H'40

Mode 3

011H'60

Mode 4

100H'A6

Mode 5

Mode 6

110H'E0

The register configuration is shown in table 3.5.

Table 3.5

Name

Abbreviation

R/W

Initial Value

Address

Frequency modification register

FMR

R/W

See table 3.4*

H'FFFFFE90

Note: * The initial value depends on the clock mode.

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