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SH7616 Datasheet(PDF) 144 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 144 Page - Renesas Technology Corp |
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144 / 935 page ![]() Section 3 Oscillator Circuits and Operating Modes Rev. 2.00 Mar 09, 2006 page 118 of 906 REJ09B0292-0200 • Modes 0–6 PLL circuits 1 and 2 halted EXTAL input or crystal resonator used (modes 0–3) CKIO input (modes 4–6) FR3 FR2 FR1 FR0 φφφφ I φφφφ E φφφφ P φφφφ CKIO 0 000 ×1 ×1/4 ×1/4 ×1/4 ×1 0 100 ×1 ×1/2 ×1/4 ×1/4 ×1 0 101 ×1 ×1/2 ×1/2 ×1/4 ×1 0 110 ×1 ×1/2 ×1/2 ×1/2 ×1 1 000 ×1 ×1 ×1/4 ×1/4 ×1 1 001 ×1 ×1 ×1/2 ×1/4 ×1 1 010 ×1 ×1 ×1/2 ×1/2 ×1 1 100 ×1 ×1 ×1 ×1/4 ×1 1 110 ×1 ×1 ×1 ×1/2 ×1 1 111 ×1 ×1 ×1 ×1 ×1 Note: Do not use combinations other than those shown above. Frequency Change: When PLL circuit 1 or PLL circuit 2 becomes operational after modifying the frequency modification register (including modification the frequency modification register in the operating state), access the frequency modification register using the following procedure, and noting the cautions listed below. Frequency change procedure • Set the on-chip watchdog timer (WDT) overflow time to secure the PLL circuit oscillation settling time (CKS2–CKS0 bits in WTCSR). • Clear the WT/IT and TME bit to 0 in WTCSR. • Perform a read anywhere in an external memory area 0–4 cache-through area. • Change the frequency modification register to the target frequency, or change the operating/halted state of the PLL circuits 1 and 2 (the clocks will stop temporarily inside the chip). • The oscillation circuits operate, and the clock is supplied to the WDT. This clock increments the WDT. • On WDT overflow, supply of a clock with the frequency set in frequency setting bits FR3–FR0 begins. In this case, the OVF bit in WTSCR and the WOVF bit in RSTCSR are not set, an interval timer interrupt (ITI) is not requested, and the WDTOVF signal is not asserted. |
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