SH7616 datasheet(147/935 Pages) RENESAS

147 / 935 page

Section 3 Oscillator Circuits and Operating Modes

Rev. 2.00 Mar 09, 2006 page 121 of 906

REJ09B0292-0200

;

φ (×4) = 62.5 MHz, Eφ (×4) = 62.5 MHz,

;

φ (×2) = 31.25 MHz, CKIO (Eφ) = 62.5 MHz,

;

MOV

#H'4E,R0

;

PLL circuits 1 and 2

→ Enabled.

;

φ (×4) = 62.5 MHz, Eφ (×2) = 31.25 MHz,

;

φ (×2 ) = 31.25 MHz, CKIO (Eφ) = 31.25 MHz,

MOV

#H'0A,R0

;

PLL circuits 1 and 2

→ Enabled.

;

φ (×4) = 62.5 MHz, Eφ (×1) = 15.625 MHz,

;

φ (×1) = 15.625 MHz, CKIO (Eφ) = 15.625 MHz,

;

MOV

#H'08,R0

MOV.B

R0,@R4

rts

nop

FREQUENCY_END:

NOP

.END

Cautions

• The read from the external memory space 0–4 cache-through area and the write to the

frequency modification register should be performed in on-chip X/Y memory. After reading

from the external memory space 0–4 cache-through area, do not perform any write operations

in external memory spaces 0–4 until the write to the frequency modification register.

• When the write access to the frequency modification register is executed, the WDT starts

automatically.

• Do not turn off the CKIO output when PLL circuit 1 is in the operating state.

• The CKIO output will be unstable until the PLL circuit stabilizes.

• When a frequency is modified, halt the on-chip DMAC (E-DMAC and DMAC) operation

before the frequency modification.

SH7616 Datasheet(PDF) 147 Page - Renesas Technology Corp

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