SH7616 datasheet(148/935 Pages) RENESAS

148 / 935 page

Section 3 Oscillator Circuits and Operating Modes

Rev. 2.00 Mar 09, 2006 page 122 of 906

REJ09B0292-0200

If PLL circuit 1 or PLL circuit 2 does not become operational after modifying the frequency

modification register (including modification in the operating state), it means that the above

procedure or cautions have not been properly observed. In this case, the WDT will not operate

even though the frequency modification register is modified.

3.2.6

Clock Modes and Frequency Ranges

The following table shows the operating modes and the associated frequency ranges for input

clocks.

Clock Input

PLL Circuit

Internal Clock*

Mode Pin

Input

Frequency

Range (MHz)

PLL1 PLL2

φφφφ

(MHZ)

φφφφ

(MHZ)

φφφφ

(MHZ)

CKIO

Output

(MHz)

0, 1

EXTAL or crystal

resonator*

8–15.625

8–

62.5

8–

62.5

8–

31.25

8–62.5

Off

8–

62.5

8–

62.5

8–

31.25

8–62.5

Off

8–

62.5

8–

15.625

8–

15.625

8–15.625

1–31.25

Off

1–

31.25

1–

31.25

1–

31.25

1–31.25

8–15.625

Off

8–

62.5

8–

62.5

8–

31.25

8–62.5

1–31.25

Off

1–

31.25

1–

31.25

1–

31.25

1–31.25

8–15.625

8–

62.5

8–

62.5

8–

31.25

—

1–31.25

Off

1–

31.25

1–

31.25

1–

31.25

4, 5

CKIO

16–31.25

Off

16–

62.5

16–

31.25

16–

31.25

—

1–31.25

Off

1–

31.25

1–

31.25

1–

31.25

1–31.25

Off

1–

31.25

1–

31.25

1–

31.25

Notes: 1. When a crystal resonator is used, set the frequency in the range of 8 to 15.625 MHz.

2. Set the frequency modification register so that the frequency of all internal clocks is 1

MHz or higher.

3. Use internal clock frequencies such that I

φ ≥ Eφ ≥ Pφ.

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