SH7616 datasheet(169/935 Pages) RENESAS

169 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 143 of 906

REJ09B0292-0200

Section 5 Interrupt Controller (INTC)

5.1

Overview

The interrupt controller (INTC) ascertains the priority order of interrupt sources and controls

interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt

which allow the user to set the order of priority in which interrupt requests are handled.

5.1.1

Features

The INTC has the following features:

• Sixteen interrupt priority levels can be set

By setting the five interrupt priority registers, the priorities of on-chip peripheral module

interrupts can be selected at 16 levels for different request sources.

• Vector numbers for on-chip peripheral module interrupt can be set

By setting the 24 vector number setting registers, the vector numbers of on-chip peripheral

module interrupts can be set to values from 0 to 127 for different request sources.

• The IRL interrupt vector number setting method can be selected: Either of two modes can be

selected by a register setting: auto-vector mode in which vector numbers are determined

internally, and external vector mode in which vector numbers are set externally.

• IRQ interrupt settings can be made (low level, rising-, falling-, or both-edge detection)

5.1.2

Block Diagram

Figure 5.1 shows a block diagram of the INTC.

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