SH7616 datasheet(173/935 Pages) RENESAS

173 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 147 of 906

REJ09B0292-0200

5.2.1

NMI Interrupt

The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by

edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either

the rising or falling edge. NMI interrupt exception handling sets the interrupt mask level bits (I3–

I0) in the status register (SR) to level 15.

5.2.2

User Break Interrupt

A user break interrupt has priority level 15 and occurs when the break condition set in the user

break controller (UBC) is satisfied. User break interrupt exception handling sets the interrupt mask

level bits (I3–I0) in the status register (SR) to level 15. For more information about the user break

interrupt, see section 6, User Break Controller.

5.2.3

H-UDI Interrupt

The H-UDI interrupt has a priority level of 15, and is generated when an H-UDI interrupt

instruction is serially input. H-UDI interrupt exception processing sets the interrupt mask bits (I3–

I0) in the status register (SR) to level 15. See section 18, User Debug Interface, for details of the

H-UDI interrupt.

5.2.4

IRL Interrupts

IRL interrupts are requested by input from pins

IRL3–IRL0. Fifteen interrupts, IRL15–IRL1, can

be input externally via pins

IRL3–IRL0. The priority levels of interrupts IRL15–IRL0 are 15–1,

respectively, and their vector numbers are 71–64. Set the vector numbers with the interrupt vector

mode select (VECMD) bit of the interrupt control register (ICR) to enable external input. External

input of vector numbers consists of vector numbers 0–127 from the external vector input pins

(D7–D0). When an external vector is used, 0 is input to D7. Internal vectors are called auto-

vectors and vectors input externally are called external vectors. Table 5.3 lists IRL priority levels

and auto vector numbers.

When an IRL interrupt is accepted in external vector mode, the IRL interrupt level is output from

the interrupt acceptance level output pins (A3–A0). The external vector fetch pin (

IVECF) is also

asserted. The external vector number is read from pins D7–D0 at this time.

IRL interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register

(SR) to the priority level value of the IRL interrupt that was accepted.

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