SH7616 datasheet(174/935 Pages) RENESAS

174 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 148 of 906

REJ09B0292-0200

5.2.5

IRQ Interrupts

An IRQ interrupt is requested when the external interrupt vector mode select bit (EXIMD) of the

interrupt control register (ICR) is set to 1. An IRQ interrupt corresponds to input at one of pins

IRL3–IRL0. Low-level sensing or rising/falling/both-edge sensing can be selected independently

for each pin by the IRQ sense select bits (IRQ31S–IRQ00S) in the IRQ control/status register

(IRQCSR), and a priority level of 0 to 15 can be selected independently for each pin by means of

interrupt priority register C (IPRC). Set the interrupt vector mode select bit (VECMD) of the

interrupt control register (ICR) to enable external input of vector numbers. External vector

numbers are 0 to 127, and are input to the external vector input pins (D7–D0) during the interrupt

vector fetch bus cycle. When an external vector is used, 0 is input to D7.

When an IRQ interrupt is accepted in external vector mode, the IRQ interrupt priority level is

output from the interrupt acceptance level output pins (A3–A0). The external vector fetch signal

(

IVECF) is also asserted. The external vector number is read from signals D7–D0 at this time.

IRQ interrupt exception processing sets the interrupt mask bits (I3–I0) in the status register (SR) to

the priority level value of the IRQ interrupt that was accepted.

Table 5.3

IRL Interrupt Priority Levels and Auto-Vector Numbers

Priority

Vector

IRL3

IRL2

IRL1

IRL0

Level

Number

000015

114

1013

112

10011

110

10968

1000767

10566

100365

10164

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