SH7616 datasheet(170/935 Pages) RENESAS

170 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 144 of 906

REJ09B0292-0200

CPU

Interrupt request

Com-

parator

Priority

decision

logic

(Interrupt request)

ICR

IRQCSR

IPRA–IPRE

VCRWDT, VCRA–VCRU

Module bus

Bus

interface

INTC

NMI

IRL3–IRL0

A3–A0

IVECF

D7–D0

UBC

H-UDI

DMAC

FRT

WDT

REF

SCIF

TPU

SIO

E-DMAC

Input/

output

control

Vector

number

Vector

number

DMAC

VCRWDT

IPR

UBC:

User break controller

H-UDI: User debug interface

DMAC: Direct memory access controller

FRT:

16-bit free-running timer

WDT:

Watchdog timer

REF:

Refresh request within bus state controller

SCIF:

Serial communication interface with FIFO

TPU:

16-bit timer pulse unit

SIO:

Serial I/O

SIOF:

Serial I/O with FIFO

E-DMAC:

Ethernet controller direct memory

access controller

EtherC:

Ethernet controller

ICR:

Interrupt control register

IRQCSR:

IRQ control/status register

IPRA–IPRE:

Interrupt priority level setting

registers A–E

VCRWDT:

Vector number setting register WDT

VCRA–VCRU: Vector number setting registers A–U

SR:

Status register

(Including EtherC

interrupt)

SIOF

Figure 5.1 INTC Block Diagram

SH7616 Datasheet(PDF) 170 Page - Renesas Technology Corp

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