SH7616 datasheet(230/935 Pages) RENESAS

230 / 935 page

Section 6 User Break Controller (UBC)

Rev. 2.00 Mar 09, 2006 page 204 of 906

REJ09B0292-0200

6.2.2

Break Address Mask Register A (BAMRA)

BAMRAH

Bit:

BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24

Initial value:

000

R/W:

R/W

Bit:

543

210

BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16

Initial value:

000

R/W:

R/W

BAMRAL

Bit:

BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8

Initial value:

000

R/W:

R/W

Bit:

543

210

BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0

Initial value:

000

R/W:

R/W

Break address mask register A (BAMRA) consists of two 16-bit readable/writable registers: break

address mask register AH (BAMRAH) and break address mask register AL (BAMRAL).

BAMRAH specifies which bits of the break address set in BARAH are to be masked, and

BAMRAL specifies which bits of the break address set in BARAL are to be masked. BAMRAH

and BAMRAL are initialized to H'0000 by a power-on reset; after a manual reset, their values are

undefined.

BAMRAH Bits 15 to 0—Break Address Mask A31 to A16 (BAMA31 to BAMA16): These bits

specify whether or not corresponding channel A break address bits 31 to 16 (BAA31 to BAA16)

set in BARAH are to be masked.

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